San Jose, Calif. -- There are a number of major holes in the IC design flow, and more research and development are urgently needed to fill them. That was the message at last week's International Conference on Computer-Aided Design here, as chip designers spoke of their difficulties in coping with reliability, power, clocking, statistical timing, verification and analog/ mixed-signal design.
ICCAD is traditionally a conference for CAD researchers, and around 80 percent of the 127 papers came from academia. But this year the organizers decided to do something different by adding a "designer's perspectives" track.
"Our goal is to bridge the gap between practitioners and research," said ICCAD general chair Soha Hassoun, an associate professor of electrical engineering and computer science at Tufts University (Medford, Mass.), in opening remarks at the conference. "We would like them [designers] to tell you [researchers] what critical issues should drive CAD research in the next few years."
Design-for-reliability needs help, several presenters said. Marek Patyra, principal component design engineer at Intel Corp., outlined several key reliability issues, including electromigration, electro- static discharge, hot-carrier injection, negative-bias temperature instability and soft errors.
Today's design automation tools address some of these issues, but all of them have drawbacks, Patyra said. "If we take the commercially available tools that feature design-for-reliability, we may end up with designs that exceed the target area, speed and power," he said. "It takes manual intervention and a lot of experience to develop a product that meets specifications and still is within reliability requirements."
Too little attention to reliability results in a fragile system, said Dennis Abts, senior principal engineer at Cray Inc., while too much effort is too expensive. Help from the EDA community is essential, he said, if design engineers are to attain a "just right" approach to reliability.
Specifically, Abts said that IC design tools now need to optimize in four dimensions: timing, area, power and reliability. Much as libraries today offer different voltage thresholds, Abts called for standard-cell libraries with varying levels of soft-error resilience. He would also like to see efficient simulation for multicore designs and verification languages that efficiently handle nondeterminism. Faced with a lack of such languages, Cray has developed its own HDL, he said.
Process variability is making statistical timing a necessity for nanometer ICs, said Fabian Klass, director of technology and manufacturing at PA Semi Inc. But statistical analysis is so slow that even small circuits can take days, he said. The challenge is to boost run-times, and tools should be "context aware" so designers know where to use statistical timing, said Klass.
Noriyuki Ito, director of the technology server division at Fujitsu Ltd., had a lengthy "wish list" for statistical analysis capabilities. He called on the EDA community to provide hierarchical statistical static timing analysis; to model interconnect variations for clock and signal wires; to supply "practical" circuits to measure process variation; to develop a method to correlate statistical timing with designs; and to create techniques for determining which part of the design is most sensitive to timing yield. At the same time, said Ito, statistical timing must not conflict with the current static timing analysis flow.
Power bedevils many nanometer chip designs, and Mondira Pant, technical lead at Intel, discussed methodologies and tools required to build a "well-behaved" power grid. Such a grid, she said, would deliver predictable voltage to all transistors throughout the chip's lifetime, and would boast low impedance and robust electromigration reliability.
Power grids are challenged, Pant said, by multiple voltage domains, low-power management techniques and the tendency to finish power grids late in the design cycle. Most issues are not found until postsilicon debug. What's needed, she said, is robust CAD tools for power grid design, analysis and verification, as well as standardized tools for IR droop prediction and electromigration verification.
Pant also called for "power grid-aware" synthesis tools, de- coupling-capacitor placement tools and droop-mitigation verification tools. "We cannot work in isolation," she said. "The design and EDA communities need to work together to develop a robust on-die power delivery system."