TAIPEI, Taiwan Foundry United Microelectronics Corp. has cleared a key 45-nanometer process hurdle by producing an SRAM chip with a bit cell size of less than 0.25 micron squared. To do it, engineers applied all the latest process tools, including immersion lithography, ultra shallow junctions, mobility enhancement tricks, and low-k dielectrics.
UMC plans to enter pilot production of 45 nm next year. It said compared to its 65-nm process, the new 45-nm process offers a 50 percent 6-transistor SRAM cell size shrink, and a 30 percent performance gain. These are the upsides.
As chip designers begin to turn their attention toward 45nm, they will need to tackle a 30 percent reduction in design rules. They must also struggle with a wide range of process variations and negotiate thorny manufacturing defects. Timing, power, signal integrity, leakage current, thermal gradients and reliability problems will continue to be challenges, too.
Like its rival Taiwan Semiconductor Manufacturing Co., the Hsinchu-based UMC used 193-nm immersion lithography scanners to enhance resolutions and improve pattern imprints on the wafer. Over the summer, TSMC said it used immersion lithography to produce a 45-nm test chip with 10 metal layers and gate lengths down to 26 nm. It also applied strained silicon, triple-gate oxide options and a second-generation low-k dielectric film that will achieve a "k" factor of 2.5 to 2.6.
UMC said its low-k film achieved a "k" factor of 2.5 in its SRAM chip.
So far, a handful of companies have revealed details about their 45-nm processes, including Intel Corp., IBM, TSMC and Texas Instruments. Chartered Semiconductor, Samsung Electronics and Infineon Technologies are all pursuing 45 nm through a technology alliance with IBM.