PORTLAND, Ore. CMOS devices isolate transistor gates from their channels with supposedly impenetrable oxides. But as chips scale below the 65-nanometer node, those oxides become so thin that applying enough voltage to turn on a transistor also enables a percentage of the electrons charging the gate to tunnel through the oxide into the channel.
"CMOS was originally adopted because it was considered to be a zero-leakage technology," said Robert Mears, founder, president and chief technology officer of Mears Technologies (Waltham, Mass.). "But gate leakage now dominates power consumption below 65 nanometers," where it can account for 70 percent of power consumed. "And as you go down the nodes, the problem only gets worse."
Mears Technologies addresses the leakage problem by adding an embedded superlattice during the construction of a transistor's channel to enhance current flow in the plane of the channel, while simultaneously blocking current flow perpendicular to the channel, thereby mitigating gate leakage. It claims its sili- con-on-silicon superlattice can reduce gate leakage by 70 to 90 percent, while increasing current drive in the channel. Founded in 1999, the company has filed 150 patents for technologies related to eliminating gate leakage.
"Gate leakage is absolutely the major problem in going to the lower nodes, and Mears appears to have an elegant solution," said Trevor Yancey, vice president of technology at IC Insights Inc. (Scottsdale, Ariz.).
Semiconductor makers have turned to new materials and exotic processing step to quell gate leakage, but Mears Technologies claims its solution is straightforward and simple.
"If Mears' technology works the way they claim it does, then it's the solution to the gate leakage problem that everyone has been looking for," said Morry Marshall, vice president of strategic technology at Semico Research Corp. (Phoenix, Ariz.). "The alternatives to Mears' technology are uncertain, expensive or outright dicey."
Those other alternatives, as proposed by the International Technology Roadmap for Semiconductors, address gate leakage with high-k dielectric oxides that insulate better, or with gates made from highly conductive metals. But transitioning to the new materials is so risky that mainstream semiconductor makers have delayed their introduction, which had been slated for 65 nm.
Mears' approach, which tweaks the existing construction methodology for the transistor channel, does not require new materials and can be added without increasing the cost of the chips, the company claims. Mears says use of its solution could extend Moore's Law at least to 22 nanometers and potentially all the way to the atomic scale.
Add it on
Mears Technologies claims its technique can be added to existing processes, including ones that have already adopted other measures to achieve performance goals at 65 nm.
Those alternatives include strained silicon, which enhances electron mobility in the transistor channel. "Strained silicon [splits] the degeneracy between light and heavy holes, or the equivalent in the conduction band, and thereby gives you a lower effective mass and higher mobility in the plane of the device," said Mears. "At 90 nm, strained silicon was successfully introduced to meet performance requirements, but as you scale down, it becomes increasingly difficult to get the same sort of performance enhancements from stained silicon."