SAN FRANCISCO The design of a one-transistor memory cell that combines a suspended gate MOSFET with a microelectromechanical gate electrode was described yesterday (Dec. 11) by researchers from ST Microelectronics (Crolles, France) and their colleagues from the Ecole Polytechnique Federale de Lausanne's Laboratory of Micro and Nanoelectronic Devices in Switzerland.
MEMS-based memories appear promising candidates for high-density nonvolatile memory. The group's scalable device shows potential in terms of power consumption, high density and speed, according to the researchers, who presented their work at the International Electron Devices Meeting here.
In the MOSFET, the contact between the movable conductive gate and the gate insulator following mechanical pull-in charges the gate dielectric. This differs from flash memories, where charges are injected into the floating gate from the channel through a thin tunnel oxide.
The drain current variation resulting from the mechanical switching from state "0" to "1" was measured to be up to 4 decades, which is conformal with the memory window of conventional flash cells, say the researchers. The memory is read through the performance of drain current measurement.
The MOSFET is programmed when a positive gate voltage is applied above the positive pull-in to write the state "1" and when a negative voltage is applied below the negative pull-in to erase the cell. When the pull-in occurs, the metal gate makes contact with the gate oxide and the electrons are extracted from the trapping centers by the positive gate voltage.
Typical switching times for these MOSFET devices are on the order of hundreds of nanoseconds. The retention times measured for this type of memory place its performance between that of DRAMs and flash memories.
The tunnel oxide has to be scaled in flash memories to ensure tunneling, but in the MOSFET the oxide does not have to be scaled, since charges are injected from the gate. The device's dynamic consumption is 6.5 microwatts per micron, which is dominated by the "0" to "1" programming step. Compared with flash memories, this MOSFET has a very low gate leakage current, significantly reducing the consumption, according to the researchers.
The researchers demonstrated cycling without significant degradation up to 105 cycles. Simulations of the device's scaling limits have shown that feasible design windows exist for the 65-nanometer CMOS node and/or by using a carbon nanotube suspended gate.
ST earlier announced a program to develop MEMS-based solid-state memories.