SANTA CRUZ, Calif. Startup Altos Design Automation, a provider of library characterization technology for static and statistical timing analysis, has announced closure of a $1.5 million round of series A venture capital financing. The round was led by veteran EDA investor Jim Hogan, who has joined Altos' board of directors.
Altos promises a ten-fold speedup in library characterization for nanometer ICs. The company introduced itself and its first product in July 2006. The product, Liberate, is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers.
The company's longer term goal, however, is generating statistical models. Altos is preparing a product called Variety that will support library characterization for statistical timing analysis.
"What Altos provides is a more thorough and broader characterization that what's available today, and a much faster speed," said Hogan. "The next big surge in EDA will be around timing and power closure, and characterization is fundamental for that." Another reason for the funding, Hogan said, is that "the founders are just a great team."
The funds will be used primarily to expand Altos' application engineering and R&D teams. Altos is also moving to a new, larger office in San Jose, Calif., in expectation of expanded operations in engineering, sales, marketing and corporate functions.
Altos was launched in January 2005 by Ken Tseng, CTO, and Kevin Chou, vice president of research and development. Both worked for CadMOS Design Technology Inc., a provider of noise analysis software, before its acquisition by Cadence Design Systems in 2001. Authors from Altos and Extreme DA discussed characterization for statistical timing analysis last year in an EEEdesign exclusive feature.