SANTA CLARA, Calif. One milliWatt per Gbit per second (mW/Gbit/s). That's the new Holy Grail for I/O power consumption in the age of multi-gigahertz signaling, according to engineers at the annual DesignCon conference that opened here Monday (Jan 28).
Rambus Inc. is expected to plow new ground toward that goal with a paper detailing a technique to deliver I/O at power rates as little as 2mW/Gbit/s. The technology will be revealed in a paper at The International Solid State Circuits Conference (ISSCC) in February.
Following not far behind, Intel Corp. engineers have prepared a paper for an upcoming IEEE circuit design conference showing techniques to hit as little as 10 mW/Gbit/s. Today's mainstream PCs using PCI Express links typically deliver I/O at power rates of 15-30 mW/Gbit/second.
The new techniques are expected to require multiple new industry standards now quietly in the works. That's in part because the work requires collaboration between circuit, chip and board designers at multiple levels.
"Co-optimization of circuits and [board-level] interconnects," is a major theme, said one engineer at DesignCon who asked not to be named.
Rising requirements for more I/O at ever faster signaling rates in mainstream electronic systems are pushing the need to find fresh techniques to lower I/O power. This year will see the first PC components ship using the new 5GHz version of PCI Express ratified earlier this year. Storage interconnects such as serial ATA and Serial-Attached-SCSI are moving to 6GHz links.
"We have to do this work or I/O power will dominate systems as we move to chips with hundreds and even thousands of pins in the future," said the DesignCon engineer.