Portland, Ore. -- Hewlett-Packard Laboratories and a trio of academic labs have scored advances that will make it easier to use nanowires as a replacement for lithography in semiconductor manufacturing, potentially taking chip making to the angstrom scale (an angstrom is 1/10 of a nanometer). Nanowires, fabricated using self-aligned superlattices to create "stamping dice," today can consistently imprint features as small as 15 nm, enabling ultrahigh-density interconnection crossbars as well as memory densities as high as 100 Gbits/cm2.
"The range of potential applications is very broad," said Stan Williams, a fellow at HP Labs (Palo Alto, Calif.). "Besides just interconnections, we can envision the crossbar structures being used as a nonvolatile memory that resides directly on any chip for configuration purposes, including holding a software kernel that doesn't require booting up [from disk]."
Researchers at the State University of New York (SUNY) at Stony Brook, the California Institute of Technology and the University of California, Los Angeles, contributed to the fabrication of ultrahigh-density nanowire-based crossbar switches made using various architectures. These crossbar switches are based on two layers of perpendicular arrays of nanowires separated by an organic film that can be switched on or off at the junctions of overlapping wires, thereby creating a programmable crossbar switch of unprecedented smallness.
"Our crossbar switch is the world's densest electrically addressable memory circuit," said Jonathan Green, a doctoral candidate at Caltech (Pasadena). "Our nanowires measure less than 17 nm wide with a 33-nm pitch, enabling us to form a 400 x 400 crossbar switch capable of storing 160 kbits in an area of about 170 square microns." Green and colleagues fabricated the crossbar in professor James Heath's lab using organic-molecular switches synthesized in professor Fraser Stoddart's lab at UCLA.
Why the interest in crossbar switches? "A crossbar is just the easiest thing to build at the nanoscale, since it's just parallel lines," said Green. "A crossbar switch is just two sets of parallel wires on top of each other, making alignment trivial."
The fabrication technique used to create the tiny lines is called a superlattice nanowire pattern transfer, or Snap, whereby molecular-beam epitaxy is used to precisely control the thickness of alternating superlattice layers of gallium arsenide and aluminum gallium arsenide. The substrate is then cut vertically, exposing the layered edge, and the GaAs is etched, leaving a precisely spaced comb structure. By depositing metal that sticks only to the teeth of the comb, parallel lines can be created with atomic accuracy.
These metal wires along the comb's teeth are then transferred from the GaAs/ AlGaAs chip to a substrate. Once there, they can serve as an etch mask to make either silicon or metal nanowires by transferring the metal line pattern to the underlying thin film like a stencil.
"The Snap fabrication process is a great technique for proving feasibility, but in our industrial lab we need to use a technique that has a higher probability of scaling up--that is, imprint lithography," said Williams of HP Labs.
The Snap-made metal lines are used to create imprint molds that can be dipped in etchant and stamped onto surfaces, resulting in line widths much smaller than can be created with even the highest-resolution photolithographic techniques. Also, the stamp can be used over and over, like the plates of a printing press.
To create the crossbar switches, two sets of nanowires must be built on top of each other. The first layer uses parallel silicon nanowires on an insulating substrate. Next comes a monolayer of switching molecules--Caltech used or- ganic rotaxane molecules. Finally, a top layer of metallic nanowires is fabricated. By sending current down one bottom wire and one top wire, a voltage potential is created just at their junction and nowhere else in the circuit. Varying that voltage controls the organic molecule between the two wires, enabling the junction to be switched from nonconducting (off) to conducting (on), as well as to read out its current state.
The organic molecules that connect selected crossbar junctions can be thought of as voltage-controlled resistors with well-defined voltages that turn the molecule on and off, as well as provide nondestructive readout by using lower voltages than are required to program it. Besides rotaxane, labs worldwide are experimenting with several other types of bistable molecules that can be used to connect the crossbar junctions. "There is currently a worldwide effort involving many research groups to define and establish the ideal nanoscale switch," said Williams.
Once a crossbar switch is fabricated, its density is beyond the capability of traditional electron-beam lithography to connect to its individual nanowires, prompting the search for alternative methods to tie nanowire crossbars to the normal-size CMOS circuitry in the rest of a chip. The Caltech group doesn't even try to link to single nanowires yet, but merely tests groups of nanowires simultaneously. "Since a nonlithographic method was used to lay down the nanowires, they are too small to individually contact," said Green. "On average, we are only able to address about three nanowires, or nine crossbar junctions at a time."
Architectures to solve this problem have been in the works for several years at the lab of professor Konstantin Likharev at SUNY, fabricated by postdoctoral researcher Dmitri Strukov. Called CMOL (for CMOS and molecular), the technique involves lithographically patterned CMOS circuitry studded with nanoposts that connect to nanowire crossbar arrays created by imprint lithography and self-assembling organic molecules.
HP Labs recently updated the CMOL approach for manufacturability by making its crossbar sparser, and thus making it easier to connect up to the CMOS layer via normal-size posts. HP Labs also moved all logic functions, including wired-ORs, into the CMOS layer. The company calls the result the field- programmable nanowire interconnect (FPNI), and predicts that this architecture could be manufactured at commercial CMOS fabs as early as 2010.
FPNI, said Williams, "is a generalization of CMOL that we can run through our fab now, and in fact we are in the early stages of doing exactly that. We hope to have prototype circuits later this year." It will be an FPGA that is eight times denser, yet uses less energy, than those currently being produced.