San Francisco -- The IC industry faces a chip design "interconnect crisis," experts warned at last week's IEEE International Solid-State Circuits Conference. The shift toward true 3-D packaging technology must be accelerated, they said.
IBM, IMEC, Intel, Qimonda AG, Samsung and others outlined 3-D packaging schemes and concepts at ISSCC, but experts agreed that the emerging die-stacking technology remains immature and expensive. Also at issue is how designers will redistribute or reduce the heat in true 3-D packages, which could house FPGAs, memories, microprocessors and even biomedical devices.
The 3-D package is a radical step up from today's chip-stacking technologies. such as flip-chip, multichip packaging (MCP) and system-in-package. Ex- perts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias or related techniques. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
More than a dozen entities are pursuing through-silicon vias and related techniques, and for good reason. Chip makers have long known that scaling can crunch the tiny aluminum or copper interconnects in IC designs, causing timing delays and other problems. The shift to copper interconnects in logic circuits and DRAMs is expected to increase unwanted copper resistivity in IC products.
The International Technology Roadmap for Semiconductors predicts the interconnect crisis could emerge as soon as 2009. Harry Hedler, principal of back-end technology for DRAM maker Qimonda, argued that the looming problem "could be avoided by through-silicon via stacking techniques."
There is some debate about this solution, however. While the silicon via technology has become more cost-effective, "it is still not there yet," said Hans Stork, senior vice president and chief technology officer at Texas Instruments Inc.
Memory will be among the first devices to deploy through-silicon vias, Stork said. But traditional wire-bonding and current chip-stacking techniques continue to make strides and may nudge out the need for true 3-D packaging. A factor in current packaging technology's favor, he said, is that it is "remarkably cheap."
3-D or bust
For years, the industry has talked about the need for 3-D packaging in applications such as cellular phones, PDAs and other small-form-factor products. Pioneers in the sector are using at least four methods to devise the chip stack: die-to-die, package-to-package, die-to-wafer and wafer-to-wafer.
There are two competing though-silicon via technologies--dry etch and laser--but a more pressing issue is whether to generate the vias in the wafer fab or the packaging house.
Several 3-D packaging and product startups, including Cubic Wafer, Tezzaron, Ziptronix and ZyCube, have emerged and are sampling products, but those offerings are "no- where near the mainstream," said Jim Handy, an analyst with market research firm Objective Analysis (Los Gatos, Calif.). "The industry is still doing wire bonding, and there is more interest in package-on-package right now."
Still, established entities such as Elpida, IBM, IMEC, Samsung and Sematech are working on the technology. Last year, Samsung Electronics developed a 3-D chip-packaging technology based on a proprietary wafer-level stack process (WSP) and through-silicon via interconnect. The company's first 3-D package houses a 16-Gbit memory solution that stacks eight 50-micron, 2-Gbit NAND flash dice and is 0.56 mm in height. WSP has a 15 percent smaller footprint and is 30 percent thinner than an equivalent wire-bonded MCP solution, the company said.
Wire bonding requires vertical gaps between dice that are tens of microns wide, with horizontal spaces on the package board that are hundreds of microns wide. WSP eliminates the need for that extra space, according to Samsung.
Instead of using a conventional dry-etching method to create the vias, Samsung taps a tiny laser to drill the holes in the chip. This reduces production cost because it eliminates the typical photolithography-related processes required for mask-layer patterning. It also shortens the process needed to penetrate a multilayer structure, said Samsung.
But the technology faces a major hurdle. "Through-silicon via is still more expensive than wire bonding," said Dongho Lee, principal engineer for the Interconnect Product and Technology Group as Samsung Memory Division.
Thus, Samsung and others continue to extend wire-bonding technology. The company recently claimed it used wire bonding to pack 16 NAND dice into a MCP that will max out at a density of 16 Gbytes. "No one knows how far wire bonding will go," Lee said.
Microprocessor vendors, for their part, are developing multicore chips and deploying repeaters within the devices. At ISSCC, Intel proposed several future scenarios, including a five-stacked-dice structure comprising a multicore processor/graphics chip, two main-memory elements, nonvolatile memory storage and an analog radio.
It is an imperfect solution, however. "Power density is a limiting factor," said Mark Bohr, an Intel senior fellow and director of process architecture and integration. "How do you remove the power?" IBM Corp. proposes putting the heat sink next to the processor in a 3-D configuration.
One driver for 3-D technology is the shift to eight-core processor products and beyond, said Wilfried Haensch, senior manager of device integration technology at IBM's Thomas J. Watson Research Center. "Power/performance trade-offs will see [multicore] systems competing with cache/memory resources at a given maximal chip size," he said.
"3-D puts a multicore processor on steroids," said Daniel Radack, staff director at the Institute for Defense Analyses, a nonprofit organization that provides research for the U.S. Department of Defense. Other devices, including analog-to-digital converters, ASICs, encryption circuits and FPGAs, also are prime candidates to go 3-D, he said. They could enable 3-D products for military and aerospace systems, such as synthetic aperture radar.
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