A "best paper" award winner at the International Symposium on Physical Design (ISPD 2007) proposes a new approach to nanometer IC variability challenges combining design optimizations with post-silicon fixes. As such, it outlines a potential new direction for design for yield (DFY) and design for manufacturability (DFM) methodologies.
The paper, entitled "Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation," was authored by Ankur Srivastava, assistant professor of electrical and computer engineering at the University of Maryland, and Vishal Khandelwal, Srivastava's graduate student. Khandelwal presented the paper at ISPD in Austin, Texas Monday (March 19).
The basic idea is to use tunable clock tree buffers that can potentially be used to fix problems after silicon is manufactured, thus improving yields. "Fixing chips that violate constraints after fabrication through tunable components means that we can be more relaxed in considering fabrication randomness at design time," said Srivastava. "In my opinion, this work will prove to be an important milestone in developing a practical design methodology that considers both design-time and post-fabrication approaches for countering fabrication variability."
The paper proposes an "integrated framework" that performs statistical gate-sizing in the presence of post-silicon tunable clock tree buffers, thus minimizing yield loss. To reduce any potential area or performance impacts of tunability, it determines the ranges of tuning to be performed at each buffer. The authors claim that, on the average, their approach resulted in a yield loss of only 3 percent.
Post-silicon tunability is not a new approach; the authors note that it was applied to Intel's Dual Core Itanium processor. Several previous academic papers have addressed post-silicon tunability. But the ISPD 2007 authors say that no existing work has tried to integrate both post-silicon and pre-silicon optimizations into one flow.
And that's where the new work comes in. Given a sequential design with a synthesized post-silicon tunable clock tree, with known tunable buffer locations, it performs simultaneous gate sizing of the combinational logic gates and timing range characteristics of each buffer, such that both yield loss and the cost of tunability are minimized.
"If we could fix all violations after fabrication, there would be no need for statistical timing analysis," said Srivastava. "But I don't think that would be too practical. Hence, doing some statistical optimization at design time and leaving the rest of the yield loss problem to post-fabrication tunability is the best approach."
Srivastava said his work is aimed at finding the "optimal balancing point" between how much post-silicon tuning is allocated, and how much design-time statistical optimization is done. The idea is to find the best possible tradeoff between tunability and the area and power penalties that come with tunable buffers.
"Of course, the testing effort would increase when we have tunability," Srivastava said. But the paper, he said, tries to balance concerns about area, power and test "in a unified way."
"This is an interesting approach to the curse of variability," said Lou Scheffer, Cadence Design Systems fellow and last year's ISPD general chair. "It is also one of the few papers I have seen that attacks statistical optimization, not just analysis. The main drawback is that it's not practical right away, since few use tunable buffers and few do speed binning. But the techniques look generally useful."