A University of Maryland professor has a radical approach to the problem of nanometer IC variability: Put it off.
By combining design optimizations with postsilicon fixes, IC yield loss can be avoided, says Ankur Srivastava, assistant professor of electrical and computer engineering.
A paper Srivastava wrote on the subject with graduate student Vishal Khandelwal received the Best Paper award last week at the International Symposium on Physical Design (ISPD) in Austin, Texas. Titled "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation," the paper outlines a method for fixing variability problems with tunable clock tree buffers after silicon is manufactured, thereby presenting a potential new direction for design-for-yield and design-for-manufacturability methodologies.
"Fixing chips that violate constraints after fabrication through tunable components means that we can be more relaxed in considering fabrication randomness at design time," said Srivastava. "In my opinion, this
work will prove to be an important milestone in developing a practical design methodology that considers both design time and postfabrication approaches for countering fabrication variability."
Srivastava's work addresses one of the biggest challenges with IC design at 65 nanometers and below--managing the impact of manufacturing variability. "Even under the best conditions, manufacturing variations of just a few atoms will result in significant differences in transistor characteristics," observed Patrick Groeneveld, chief technologist at Magma Design Automation Inc. (San Jose, Calif.). "Unless addressed, the increased variability will lead to significant yield loss at 45 nm and below."
As a result, EDA vendors and academics have come up with a number of presilicon solutions, such as statistical timing analysis, gate sizing and buffer insertion. Many new design-for-manufacturability tools also focus on managing variability and avoiding yield loss.
The ISPD paper doesn't rely on postsilicon fixes alone. Since tunable buffers carry area and performance penalties, the idea is to minimize those penalties by running a statistical optimization during design, so as to determine the range of tuning that can be performed at each buffer. The authors claim their approach resulted in an average yield loss of only 3 percent.
Postsilicon tunability is not a new approach; Srivastava and Khandelwal note that it was applied to Intel Corp.'s dual-core Itanium processor. But the pair say that no previous work has attempted to integrate both postsilicon and presilicon optimizations into one flow.
And that's where the new work comes in. Given a sequential design with a synthesized postsilicon tunable clock tree, with known tunable buffer locations, the paper proposes simultaneous gate sizing of the combinational logic gates and timing-range characteristics of each buffer, thus minimizing yield loss and the cost of tunability.
"If we could fix all violations after fabrication, there would be no need for statistical timing analysis," said Srivastava. "But I don't think that would be too practical."
Srivastava said his work attempts to find the "optimal balancing point" between postsilicon tuning and design-time statistical optimization. The idea is to achieve the best possible trade- off between tunability and the area and power penalties that come with tunable buffers.
"Of course, the testing effort would increase when we have tunability," Srivastava said. But the paper, he said, tries to balance concerns about area, power and test "in a unified way."
The ISPD paper presents "an interesting approach to the curse of variability," said Lou Scheffer, a Cadence De- sign Systems Inc. fellow.
"Suppose you add to your design some buffers that can be tuned after manufacturing, like DRAMs do to weed out bad rows and columns," Scheffer said. "These will presumably be quite a bit larger and more expensive than conventional buffers. Therefore, given speed targets, you'd like to size all your gates such that the tuning range needed for the tunable buffers is minimized.
"The main drawback is that it's not practical right away, since few use tunable buffers and few do speed binning," Scheffer said. "But the techniques look generally useful."
According to Magma's Groeneveld, Srivastava and Khandelwal's paper addresses the design-for-yield challenge "in a novel and innovative way." The core contribution of the paper, he said, is the methodology of simultaneous clock tree gate sizing and buffer range selection. Postsilicon tunable chips "would allow a much improved yield," Groeneveld said.
"Further research work is required to evaluate this design trade-off, but the proposed application to clock tree tuning looks promising," he said.