SAN JOSE, Calif. Intel tipped more details about its Itanium processors today, committing to use of a new high-speed interconnect on the high-end server microprocessors starting in 2008. Ultimately, the so-called Common System Interconnect (CSI) will appear in both Itanium and Xeon server CPUs.
Tukwilla, Intel's code name for a four-core Itanium processor due in 2008, will be the first to use CSI instead of a traditional Intel front-side bus to link to external components. The new CPU is expected to double the performance of Intel's existing 9000 series Itanium, a two-core chip code named Montecito.
The new Itanium CPU is expected to sample this year and will also use a form of simultaneous multi-threading expected to support two threads per core. The technique is similar to the HyperThreading approach Intel discontinued.
Jim Fister, a technology strategist in Intel's Digital Enterprise group, sketched out the Itanium roadmap in a keynote address at the Gelato Ice conference here Tuesday (April 17).
Intel has been criticized for maintaining Itanium as a separate architecture aimed at the rarified market for mainframe-class systems. Fister defended Itanium which he said now shares about an equal slice of a $25 billion market for high end servers with Sun's Sparc and IBM's Power processors.
Fister gave few details about CSI except that it is aimed to leapfrog existing interconnects such as HyperTransport used by archrival Advanced Micro Devices. CSI should have "much higher performance" than Intel current front side bus running at up to 1.3 GHz on its Xeon processors.
Intel wants CSI to embrace two different approaches to linking processors in high-end servers. It should enable coherent data transfers between small groups of local processors as well as non-uniform memory links between as many as 128 CPU over a more widely distributed system. The later capability may require a software abstraction layer to reconcile different levels of memory latency within a system.
The company is now evaluating in the lab some of its first CPUs made in its 45nm process technology. Based on their performance, Intel expects to disclose more details about CSI as early as this summer.
Although both Intel's Itanium and Xeon server CPUs ultimately will use the CSI interconnect, OEMs will not be able to design systems, at least initially, that could accommodate either CPU due to other differences in the architectures. "Long term that [plug and play capability] would be great to have," said Fister.
Intel will follow up Tukwilla with Paulson, which may use between 6 and 10 cores in a CPU that has no announced shipping date yet. It is expected to double performance of Tukwilla.
Intel is likely to use 65 and 45 nm process technology respectively for the two Itanium generations, although it has not yet announced in what processes the chips will be made.
In the short term, Intel plans to release later this year an upgrade of its current Montecito Itanium chip. The Montvale CPU will boost its front side bus to 667 MHz and support demand-based switching, a capability for dynamically lowering processor power based on changing workloads.
Separately, Intel launched a range of new products and initiatives at its Intel Developer Forum in Beijing. The company also announced quarterly results that showed revenues down slightly, but profits that have increased.