SHANGHAI Samsung Electronics is unveiling an all-DRAM stacked memory package using direct metal connections between chips, which the company claims is the first of its kind in the memory realm. Samsung expects the new stacked package design will satisfy increasing demand for high density, high performance chips needed in next-generation computing systems in 2010 and beyond.
The device consists of four 512 megabit DDR2 DRAMs that total 2 gigabits. Samsung said it can make up to 4 gigabyte DIMM with the new approach, which reduces package size and power draw. The company did not provide specific metrics.
"The performance advancements achieved by our (wafer scale package) technology can be utilized in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory," said Tae-Gyeong Chung, vice president of Samsung's Interconnect Technology Development Team.
Samsung did not indicate a commercial schedule for introduction of the device. But news of it comes shortly after IBM Corp. said it will sample its first commercial devices to make direct metal connections between chips this year.
In 2008, IBM will sell production quantities of a power amplifier that sports as many as 100 direct metal links to a power ground plane. That could lower power consumption by as much as 40 percent for a device that is a key component in cell phones and Wi-Fi adapters.
Currently, memory die in multi-chip packages are connected by wire bonding. That requires a vertical space buffer between dies that Samsung said is tens of microns deep. Horizontal spacing is also required on the package board that is hundreds of microns wide for the die-connecting wires.
To eliminate these spacing gaps, Samsung used lasers to cut micron-sized holes through the silicon vertically and then added in copper to connect the memory circuits. The technology is known as "through silicon via," or TSV.
Inside the wafer scale package, Samsung said the TSV is housed within an aluminum pad to escape the performance-slow-down effect caused by the redistribution layer. Citing the complexity of DRAM stacking, the company said this was "a much more difficult engineering feat" than that accomplished last year when it unveiled a wafer scale package using NAND flash dies.
Samsung said its TSV memory device allays fears over performance degradation in multi-chip packages with high-speed memory chips operating at speeds of 1.6Gbits per second or more.