Samsung Electronics scored a win last week in what is shaping up to be an industrywide effort to accelerate the development of direct metal connections between chips. Samsung completed the task in an all-DRAM stacked package--the first of its kind, according to the company.
Samsung expects the stacked-package design will satisfy the increasing demand for high-density, high-perfor- mance chips needed in next-generation computing systems in 2010 and beyond. The device consists of four 512-Mbit DDR2 DRAMs, for a total of 2 Gbits. Samsung said it can make up to a 4-Gbyte dual in-line memory module with the new approach, which reduces package size and power draw.
The company did not provide specific metrics or disclose its intentions for the technology. The company said it did not have a commercial schedule for introduction of the device. But, not surprisingly, it did say it expects direct-metal-link technology will pop up in a variety of packages, especially system-in-package solu- tions that combine logic with memory.
Earlier this month, IBM Corp. said it would sample its first commercial devices to make direct metal connections between chips this year (see April 16, page 1). In 2008, IBM will sell production quantities of a power amplifier that sports as many as 100 direct metal links to a power ground plane. That could lower power consumption by as much as 40 percent for a device that is a key component in cell phones and Wi-Fi adapters.
More companies will soon start touting their "milestones" in direct metal connections as well, said Trevor Yancey, an analyst with IC Insights. "Integration in the vertical direction, such as chip stacking, is a trend that continues to gain momentum, and successful implementation of through-silicon vias will make the technology even more attractive."
Currently, memory dice in multichip packages are connected by wire bonding. That requires a vertical space buffer between dice that Samsung said is tens of microns deep. Also required is horizontal spacing on the package board that is hundreds of microns wide for the dice-connecting wires. To eliminate those spacing gaps, Samsung used lasers to cut micron-size holes through the silicon vertically, and then added copper to connect the memory circuits. The technology is known as through-silicon via, or TSV.
Inside the wafer-scale package, Samsung said, the TSV is housed within an aluminum pad to escape the performance-slowdown effect caused by the redistribution layer. Citing the complexity of DRAM stacking, the company said this was a much more difficult engineering feat than that accomplished last year when Samsung unveiled a wafer-scale package using NAND flash dice.
"The via hole for the TSV technology was applied to the scribe lane of the NAND flash," said Tae-Gyeong Chung, vice president of Samsung's interconnect technology development team. But for a DRAM, that approach "would result in a performance slowdown due to the complexity of rerouting the design from the edge of the DRAM die to the center pad," he said. "Therefore, the via hole is better located right on the aluminum pad."
Bob Merritt, a DRAM analyst at Semico Research, said the number of active signals that need to be processed is also a factor. "There are a total of 19 active signals for the x8 NAND," he said, vs. "a total of 52 for the x8, 512-Mbit DRAM."