The road map to advanced semiconductor nodes calls for ultralow-k dielectrics to reduce parasitic capacitance between adjacent metal lines, especially on interconnection layers, at the 32-nanometer node and beyond. Now IBM Corp. has vowed to commercialize the ultimate dielectric--a pure vacuum--between metal lines of its 32-nm chips, thereby reducing parasitic capacitance on interconnection layers by 36 percent.
"IBM's air gap-enhanced dielectric is now the plan of record for their 32-nm node," said David Lammers, director of WeSrch.com. "That means it's also on the 2009-2010 road map for all its research partners, including AMD, Sony, Toshiba and Freescale--they are now all committed to air gap at 32 nm."
IBM has already converted its state-of-the-art manufacturing line in East Fishkill, N.Y., to air gaps and has fabricated a next-generation Power6 microprocessor that reaps a 10 to 15 percent system-level performance enhancement from the technology. IBM hopes that by 2010, further optimization will increase system-level performance by as much as 30 percent or generate 30 percent less heat, for cooler operation at the same performance level.
"Air gap" is a misnomer, since instead of air the technique literally vacuum-packs interconnection layers to reduce their parasitic capacitance, the bane of power-hungry advanced nodes. Air gaps are formed by adding a maskless process step that uses a polymer-based nanomaterial to etch out the dielectric between the most tightly spaced lines on the metallic interconnection layers, thereby reducing their parasitic capacitance. IBM's proprietary polymer self-assembles trillions of uniform nanoscale holes across an entire 300-mm wafer, through which IBM etches air gaps between the metal lines, displacing most of the dielectric.
"The real breakthrough is our use of a self-assembling nanomaterial," said IBM fellow Dan Edelstein, chief scientist on the air gap project. "We have invented and perfected a material that self-assembles into 20-nm structures--five times smaller than we can produce with lithography. We use these structures to create air gaps between very, very tight wiring dimensions."
In 1997, Edelstein architected the copper interconnect that has since become an industry standard. Likewise, Edelstein predicts that other chip makers will have to adopt IBM's vacuum-packing method if they are to remain competitive.
"Air gap technology is as big a breakthrough as copper interconnects was," said John Kelly, senior vice president and group executive for technology in IBM's Systems & Technology Group. "Everybody went to copper interconnects, and everybody is going to go to air gap as soon as they figure out how to do it."
"Using holes, or what IBM is calling air gaps, to decrease capacitance is not really a new thing--people have been proposing it for over a decade," said Mike Mayberry, director of components research at Intel Corp.
Intel, he said, "does not anticipate going to air gaps at this time, because we've done some experiments and some modeling and found two key problems: These holes transfer mechanical stress from one place to another, which can cause failures, and secondly, you can cause further reliability problems with lower layers as you drill down from above."
In Mayberry's view, "These problems make air gaps look unattractive at this time. But there may be better ways of making them, so we will continue to evaluate them."
Intel is also continuing to evaluate options for low-k dielectrics, he said.
"We are currently carbon-doping our silicon oxides to loosen up their lattice, which is like putting in little, 2-nm air gaps we call pores. Carbon doping gets our current low-k dielectric constant down to below three. And we are evaluating several options for increasing the size of these pores, such as by building the pore into the dielectric molecule [instead of doping, which introduces the pores by making defects in the lattice] or by going to a polymer like Teflon, which has a dielectric constant in the low twos."
Intel, Toshiba, Sony and many other companies have experimented with air gap technologies to reduce parasitic capacitance at advanced nodes, but IBM claims that its nanomaterial was the key enabler that makes vacuum-packing interconnection layers practical.
"There have been plenty of experimental papers on air gap technology, but the difference here is that we have invented a polymer that enables air gaps to be commercially practical, plus we are demonstrating it on an existing functional microprocessor to prove it works," said Edelstein. "We have also mastered the polymer synthesis process and are capable of providing high-volume quantities of this nanomaterial to our fabs, which will use it just like a typical photoresist, with the same tooling and protocols."
The polymer works by self-assembling into a porous matrix full of tiny, 20-nm holes through which the dielectric between interconnection lines can be etched away and replaced with a pure vacuum. A vacuum has the lowest possible dielectric constant--theoretically as low as 1.0, if all the dielectric between metal lines is removed. In this case, however, just enough air gap was etched to reduce the dielectric constant to 2.0. By comparison, the best porous low-k dielectrics today have a dielectric constant of 2.4.
"For the last 40 years, we have used glass as insulators for interconnects with a dielectric constant [or "k" value] of four," said Kelly. "For 40 years, the whole industry has struggled very hard to get the dielectric constant below three, and here we are reducing it to two--which will give us a huge leap in performance and a new way to extend Moore's Law."
Kelly claimed that two generations of Moore's Law wiring-performance improvements could be reaped in a single step by going to air gaps. The polymer step can be inserted into the standard processing flow in any CMOS fab, IBM claims, by merely loading its polymeric nanomaterial instead of ordinary photoresist, resulting in gaps between the metal lines with an ultralow-k dielectric constant of 2.0.
"The polymer works like photoresist used as an etching template--it's sacrificial. We just use it to create an initial pattern of tiny holes, 20 nm in diameter, that we etch into the existing glass insulator," said Edelstein. "Then we have a trick that melds the holes together into a single air gap between the lines. The last step is to cap the air-gapped layer with the next layer of dielectric."
The reason that IBM has chosen air gaps over low-k dielectrics is not just for the low "k" value they provide, but also because air gaps don't add any new materials into the makeup of its chips. Intel, for instance, reports that it is experimenting with a low-k material that has a dielectric constant of 2.4. IBM, on the other hand, has chosen not to introduce such a new material, and to confine air gap technology to processes that can be performed by standard semiconductor processing equipment.
"We do everything you would normally do to create the wiring levels with no change whatsoever, then we just add a few processing steps after each interconnection layer to form the gaps--basically removing the insulator from between the metal lines and then sealing off the whole layer to retain the vacuum," said Edelstein.
The biggest unknown for IBM is how the new hollow internal structures on air-gapped layers will affect chip reliability. So far, IBM claims the main limitation is in the number of layers you air-gap--you cannot do a whole chip without adversely affecting reliability.
The air gap process was developed jointly at IBM's Almaden Research Center in San Jose, Calif., and the T.J. Watson Research Center in Yorktown Heights, N.Y. The College of Nanoscale Science and Engineering of the State University of New York at Albany also worked on the nanomaterial, in concert with IBM's Semiconductor Research and Development Center in East Fishkill.