When NXP Semiconductors started to use advanced low-power IC design techniques, it was in for a surprise. "In some cases, we have experienced a twofold productivity drop for the implementation phase," said Hervé Menager, design and technology officer at NXP.
That's far from a unique experience. While EDA vendors have been fighting over two competing low-power specification format standards, a larger problem may have been obscured: Low-power techniques such as multivoltage design are so difficult that a rethinking of the entire IC design flow may be needed. Menager and other IC designers provided an inside look at the challenges at the recent Electronic Design Process (EDP) workshop in Monterey, Calif.
EDA vendors acknowledge designers' dilemma. "The productivity impact is huge," said Eric Filseth, corporate vice president of Encounter marketing at Cadence Design Systems Inc. "[Low-power] techniques are not tweaks to layout. This is architectural stuff. It touches the whole design phase--verification, implementation, test, everything."
Most observers agree that basic low-power design techniques such as clock gating and multiple voltage thresholds are well-established and supported by existing tools. Clock gating reduces dynamic power by restricting clock distribution. Multiple-voltage-threshold (multi-Vt) designs use high-Vt cells to decrease leakage current where performance is not critical.
Where designers run into difficulty is with more-advanced, multivoltage techniques. With a multivoltage supply (multi-Vdd) approach, some blocks use lower supply voltages than others, creating voltage "islands." It's complex enough when the supply voltages are static, and even more complex when dynamic voltage scaling is used to change the supply voltage level during operation.
To save leakage, some designs use power gating to shut down blocks that aren't in use, using multiple-threshold CMOS (MTCMOS) switches. The power-down and power-on sequences can be extremely complex to design and verify.
The advanced techniques are catching on. In a survey conducted at the 2006 Design Automation Conference by Sequence Design Inc., 26 percent of respondents said the were using clock gating, and 24 percent said they used multi-Vt libraries (see chart, page 1).
"Advanced techniques like multivoltage and power shutdown impact the entire design flow," said Gal Hasson, director of marketing for RTL synthesis and low-power products at Synopsys Inc.
Thus far, Menager said at the EDP workshop, NXP has attacked dynamic power by trying to reduce power dissipation through clock gating and by minimizing switching capacitances. More recently, he said, the company has started to use voltage islands and frequency scaling to meet both performance and power goals.
Multivoltage designs typically require level shifters, which let signals cross power domain boundaries; retention registers, which retain state information during power-down; on-chip switches, which turn power on or off; and isolation cells, which control outputs when power is shut down. NXP uses these techniques, but specifying intent for the automated implementation and verification of the circuit elements is complex, Menager said.
Level shifters, for example, introduce layout constraints that Menager said "can dramatically increase the complexity of the CAD tools." Layouts can be logically correct but physically wrong, he said.
When isolation clamps are used for power switching, Menager said, it's possible to propagate unwanted data, and a floating input will potentially generate a short circuit. Retention registers may require always-on buffer trees to the control signals, and the connection of power supplies is "error-prone and time- consuming," he said.
Voltage islands can be turned on or off with on-chip switches, but those make power distribution and floor planning more complex, Menager said. Switches need proper sizing to balance current-carrying capability against area and leakage. Static IR drop analysis is necessary to verify that sizing.
At the system-on-chip (SoC) level, Menager said, global buffering strategies and power distribution are complex. Multiple power domains can cause the number of corners in static timing analysis runs to "explode" when min/max voltage combinations from all the power domains are considered.
Low-power design strongly affects design-for-test (DFT), Menager noted. The insertion of scan chains across voltage islands raises a number of complications.
"We want scalable solutions that are less disruptive to back-end implementation," Menager said. "One important part of that is to capture power network intent. It has to be captured properly early on."
A common power format is crucial for capturing power intent, and Menager said NXP has used the Silicon Integration Initiative (Si2) Common Power Format (CPF) and found it valuable. But the standards war between CPF and Accellera's Unified Power Format (UPF) is a problem.
"The good news is that we went from no format to some format," Menager said. "The bad news is we went from none to one too many."
When clocking gets complex
Multivoltage techniques are also in use at Freescale Semiconductor Inc., where GSM cell phone standby current and active current are decreasing at about 15 percent per year, said design manager Milind Padhye. With multivoltage design styles, Padhye said, the unused portion of a design can be switched off, and the low-performance portion can run at a lower voltage. But there's a cost.
"Clocking is a major challenge for multivoltage designs," Padhye said. "The voltage starts shifting the clock. As the clock starts shifting, your timing goes haywire. You can end up with hundreds of corners to optimize the timing."
Architectural analysis is required to achieve efficient voltage partitioning, Padhye said. And then the system must be verified multiple times--during the power-off process, after power-off has completed and during power-up.
"Let's say you created a transaction that ended up in a power-down [state], and now the chip is dead," Padhye said. "How do you debug it? It's like asking a dead man, 'Can you please tell me how you died?' " Padhye asserted that avoiding one power bug is the equivalent of avoiding 10 functional bugs.
With retention verification, designers must verify that the state was saved correctly, that the state was restored correctly and that the system can function after power-up. With voltage and frequency variation, designers must verify system performance state, voltage change, system operation during the change and system operation after the change.
Padhye said it's critical to support low-power techniques consistently throughout the flow. To that end, Freescale is using CPF but wants the industry to adopt one power format, Padhye said.
Higher abstraction level
Texas Instruments Inc. fellow Mahesh Mehendale also argued for a system-level approach to low-power design. His EDP presentation offered an overview of low-power design challenges for a multistandard, multiformat video processor SoC.
At the SoC level, Mehendale said, TI's power management strategies include adaptive voltage scaling, which minimizes voltage based on process and temperature; dynamic power switching, which switches between power modes to reduce leakage; dynamic voltage and frequency scaling, which adjusts voltage and frequency to adapt to performance needs; multiple voltage domains; and static leakage power management.
The trick, said Mehendale, is finding the "power optimal" operating point between frequency and common collector voltage. Lower Vcc helps both dynamic and leakage power, but if Vcc is lowered while keeping the frequency the same, the gate count will go up, negating any power savings, he said. If chosen at the architectural level, Mehendale said, the optimal MHz/Vcc trade-off can drive the need for parallelism and pipelining.
"Power needs to be addressed at all levels of abstraction," Mehendale said. "The impact at the system and architectural level is significantly higher."
Major providers of IC implementation tools--including Cadence De- sign Systems, Synopsys Inc. and Magma Design Automation Inc.--all say they're improving their support for advanced low-power design techniques. Earlier this year, Cadence introduced a low-power design flow based on CPF, which Cadence developed and is pushing as a standard. Cadence's flow brings power awareness to synthesis, verification, formal equivalency checking, DFT and physical layout.
What Cadence doesn't offer today is a system-level low-power design capability. "It's a natural thing to do," Filseth said. "This is where the major power savings are to be achieved--the architectural and system level."
At Synopsys, all synthesis optimizations, including DFT, are "power aware," Hasson said. To support multivoltage design, he noted, Synopsys' synthesis tools can infer retention, isolation and level-shifting cells. In physical implementation, Synopsys' power network planning tools can run an IR drop analysis, and its layout tools can place power switches correctly.
Magma Design Automation has offered an integrated low-power design flow for two years, said Arvind Narayanan, product manager for low-power products. "The multiple-Vdd flow that Herve [Menager] talked about is automated within the system," he said.
Low-power design support will be an EDA priority for years, vendors say. "This is not a bump on the side of existing tools," Filseth said. "This is a whole rethinking of how the design flow works."