The Accellera standards organization announced Friday (May 11) its approval of the Standard Co-Emulation Modeling Interface (SCE-MI) version 2.0, a specification that provides a way to link transaction-level models to hardware acceleration, emulation, and rapid prototyping platforms. The new version claims to offer a faster, better, and more up-to-date interface.
The earlier SCE-MI 1.1 specification was approved by Accellera in May 2005. The standard is under development by Accellera's Interface Technical Committee (ITC), whose stated mission is "to identify and standardize multi-abstraction and multi-domain interfaces that enable complete, high performance verification environments to be constructed."
SCE-MI is "a common interface where you can connect high-level models with a hardware accelerator or emulator," said Shrenik Mehta, Accellera chair. "The idea is that you get hardware acceleration that can run very fast." Further, he noted, SCE-MI provides a common interface that fosters tool interoperability, and will allow users to run the same models with any accelerator or emulator that supports the standard.
SCE-MI 2.0 promises backwards compatibility with the previous version. It adds a streaming interface with data shaping to optimize emulation speed. It also provides increased options for model migration, and offers simplified transactor modeling. "For people writing models, this is a cleaner interface," Mehta said.
Further, Mehta noted, SCE-MI 2.0 provides updated support for industry-standard languages. While the previous version worked with Verilog, SCE-MI 2.0 supports the SystemVerilog Direct Programming Interface (DPI). The new version also adds compatibility with the Open SystemC Initiative Transaction Level Modeling (TLM) definition.
Vendors represented on the ITC include AMD, Cadence Design Systems, Mentor Graphics, and Broadcom. One company that's already announced support for SCE-MI 2.0 is Mentor Graphics, which rolled out its Veloce emulators and accelerators last month. Mentor uses SCE-MI 2.0 to enable what it calls "transaction-based acceleration," which provides a way to compile and test designs from transaction-level testbenches and requires no connection to physical hardware.