In a drive to make it easier for FPGA and pc-board designers to work together, Zuken and Aldec are announcing a partnership that will make it possible to launch Aldec's FPGA design tools from within Zuken's CR-5000 pc-board design environment. The companies will set forth a roadmap at the June Design Automation Conference (DAC).
Aldec provides Active-HDL, an FPGA design suite that includes mixed-language simulation. Zuken's CR-5000 design suite offers a constraint-driven environment from schematic capture through board layout. These are complimentary products, said Nik Kontic, Zuken technology partner.
"The problem for the customer base has been how to concurrently work with FPGA design and PCB design," Kontic said. "As you develop your FPGA and go through several iterations, the pin assignment changes." This pin assignment must be passed to the board designer, who may have constraints that need to be passed back to the FPGA designer, Kontic noted.
The initial development of the partnership allows users to launch Active-HDL from within the CR-5000 System Designer schematic environment. This makes it possible to perform FPGA timing simulation for the complete design, rather than for individual FPGAs in isolation. The ability to pass pin assignment information back and forth is currently under development, Kontik said.
Currently under discussion, Kontik said, is an ability to launch Active-HDL from the CR-5000 Board Designer layout environment. This would make it possible for layout engineers to perform pin swaps that concurrently update all pc-board and FPGA design data, rather than only being able to perform this on request from the FPGA designer.
No timetables have been given for deliverables under the partnership, but Zuken and Aldec will discuss the "scope, plans and vision" at DAC, Kontik said.