As more and more chip designers tackle their first low-power designs, they're finding that tools and silicon intellectual property (IP) aren't enough. What's needed is a common methodology and that's what Synopsys Inc. and ARM Ltd. are claiming to define in an upcoming Low Power Methodology Manual (LPMM).
The authors hope the manual, published by Springer Science+Business Media LLC, will represent a major step forward for low power IC design. The comprehensive manual takes a hands-on approach by describing best practices, offering recommendations, and citing warnings about design pitfalls. It comes at a time when designers are
struggling with multi-voltage design techniques like power gating and dynamic voltage and frequency scaling, both of which are extensively described in the LPMM.
Preview copies of the LPMM will be available at next week's Design Automation Conference, and the manual will be discussed at a Wednesday lunch event sponsored by Synopsys and ARM. Low power design will be a prominent theme at the conference, where new technology will debut for multi-voltage verification and low power synthesis.
"Establishing a common methodology in the industry has a huge value," said Michael Keating, Synopsys fellow and LPMM co-author. "With power gating in particular, a number of people are doing it very well, but it's still a challenge to the mainstream design community. If we can help make it more mainstream by capturing best practices and describing a general methodology we can all adhere to, we will provide value."
Keating was also a co-author of the Reuse Methodology Manual (RMM), a guidebook from Synopsys and Mentor Graphics published in 1998 that helped establish a methodology for silicon IP reuse. While the LPMM involved a broader collaboration among more people, the basic approach is the same as for the RMM, Keating said: "to be as practical as possible, to bring together best practices, and to publish ways in which the general engineering public can take advantage of emerging technology."
David Flynn, ARM fellow, is the other primary author of the LPMM. As an IP provider, Flynn noted, ARM has an interest in making technologies like power gating and voltage scaling available to its customers. "We have expert customers who do this really well, but they weren't telling anyone else, and they typically had an internal flow they could hide away," he said.
In a separate but related announcement this week, Synopsys and ARM are also announcing the availability of an implementation reference methodology for the ARM1176JZE-S synthesizable microprocessor. The methodology, available to licensees of that processor, provides scripts and documentation for implementing aggressive power management techniques including power gating, multi-threshold voltage optimization, and dynamic voltage and frequency scaling.
The LPMM is the outcome of a decade-long collaboration between Synopsys and ARM, Keating and Flynn said. The two companies worked together in 1998 to develop the first synthesizable ARM7 core. The companies then engaged in technology demonstration projects, culminating in the Synopsys ARM low-power technology demonstrator (Salt) project, which resulted in working silicon late last year. That project employed clock gating, multi-voltage, dynamic voltage scaling, and power gating.
"Once we wrapped up that [Salt] chip, we cranked out the book, which is a combination of theory behind what we did and a description of the project itself," Keating said. "We wanted to do a hands-on project ourselves so we could gain experience we really can't get from reading academic papers or talking to customers."