SAN JOSE, Calif. Texas Instruments Inc. Wednesday (June 13) entered the high-k dielectrics arena, announcing plans to integrate this material for its high-performance chips at the 45-nm node.
TI (Dallas) plans to use high-k for gate-stack applications, as traditional silicon oxide materials are running out of gas. For years, high-k dielectrics have been under consideration to address leakage and power in chip designs.
The chip maker also plans to deploy metal gates at 45-nm, but TI did not elaborate on the specifics. Meanwhile, TI will first deploy its high-k materials on the microprocessor front, reportedly for Sun Microsystems Inc.'s Sparc devices. TI manufacturers Sparc chips on a foundry basis for Sun (Mountain View, Calif.).
In its approach, TI will leverage a chemical vapor deposition (CVD) process to deposit hafnium silicon oxide (HfSiO), followed by a reaction with a downstream nitrogen plasma process to form HfSiON or hafnium silicon oxynitride.
The technology will reduce leakage by more than 30 times per unit area, as compared with commonly used silicon oxide materials for gate dielectrics, said Ben McKee, vice president of CMOS development at TI.
TI's high-k film will enable the chip maker to scale its devices at 45-nm and beyond, McKee said.
Last June, TI unveiled details of its 45-nm process, but the company did not mention its high-k technology. The chip maker expects to sample a 45-nm wireless product in 2007, with qualified production starting by the middle of 2008.
High-k dielectrics will be added in later versions of the 45-nm process for TI's high performance products. A MPU-class product is ''expected to be the first process to integrate the high-k material,'' according to TI.
That could mean Sun's Sparc devices. TI's own devices are expected to follow, ''depending on the time and product,'' McKee said.
IBM, Intel and NEC have separately announced processes that make use of high-k. TI claims to have some advantages in high-k.
''By implementing the nitrided CVD technique, TI is able to solve the leakage issue without degradation of the other key parameters that customers have come to expect from SiO2-based gate dielectrics,'' according to the company.
''Through a modular addition to the typical CMOS gate stack process, HfSiON integration has been demonstrated offering mobility that is 90 percent of the silicon dioxide universal mobility curve, with effective oxide thicknesses (EOTs) below 1-nm,'' according to TI.
In recent times, TI has tweaked its fab strategy. Moving to remain competitive in what has become a brave new world of IC manufacturing, TI recently disclosed the details of its revised "hybrid" fab strategy. The chip maker is bolstering its in-house efforts in analog production, but it is also shifting more of its logic-based IC work and process flow to the foundries.