A funny thing happened on the way to the "everything-is-handheld" world of computing and communications: turns out Moore's Law doesn't apply to batteries. While transistor counts are still doubling roughly every 18 months, the same progress in battery life takes more than five years.
But power issues go beyond the battery. Problems relating to power consumption affect every system-on-chip (SoC) design at 90nm and below. Traditional tradeoffs between performance and area are compounded by the addition of power into the equation. High on-chip currents decrease the life and reliability of products, so reducing power has become a critical challenge for the nanotechnology era and one of the most important success factors for new SoC designs.
The true cost of power in SoC design is often difficult to quantify, but you can make a pretty fair estimate of the direct and hidden costs of power and their impact on engineering, NREs, parts and packaging, yield and reliability, time to market, and market competitiveness.
Engineering costs are a function of time, and there are numerous power-induced problems in SoCs such as high leakage current, IR drop, process variation across the die, wire delay modeling, and crosstalk noise, which are responsible for increasing NREs. For example, when reducing power at the gate level, designers perform a number of iterative steps from RTL changes, to synthesis, to power checks, and back to RTL changes, thereby increasing the engineering time. Our conservative estimates are that this adds about $200,000 annually to NREs.
It's becoming more common to simultaneously craft an IC, package, and board while sweating power requirements for all. So designers must account for IR voltage drops in the package and include them in the overall design optimization. Designers choose the IC package early in the design and the power specification is communicated to the customer.
An increase in power by 1 watt increases the package cost by $1; for 2 watts the price of a package rises by $5. But beware! Choosing the wrong package, perhaps based on price alone, might lead to a lot of bad parts and a big hit on a company's reputation.
Power plays a very important role in determining the cost of the end product as it includes the power supply costs. The growth of mobile applications is putting more and more pressure on the consumer and wireless markets for products whose power supply/battery life run for several hours, so power is one of the key differentiators for positioning the product.
For instance, a laptop battery's capacity is 2,500 to 4,000 milliAmp hours. With the "pedal to the metal," you can use as much as 2,500 milliAmps per hour, or 1-2 hours of productive work time. The key "consumers" of the laptop battery are the processor, the screen, wireless networking cards, drives, and other peripherals. The more these functions are used, the faster your laptop battery will run out of juice.
Time to market (TTM) is a critical competitive metric for most market segments. TTM is important in industries where products are outmoded quickly. TTM is not only critical in beating competitors to market but it also impacts the overall cost of the project. The longer it takes getting a product to market the greater the impact to market share. In fact, every month a product is delayed costs the company a 14 percent loss in market share, and the intricacies of power-aware design are a growing factor in these delays.
Calculating the true cost of power isn't an exact science, but every SoC designer and their manager understands it can be a big number in today's competitive marketplace. Managing these costs requires sound planning, since it's a given that problems will arise. You need to employ the right tools and technologies to manage power consumption while also accounting for its corrosive effects on other parts of the design. It's a top-down approach that will make your bottom line look good.
Vic Kulkarni is president and CEO of Sequence Design.