Kyoto, Japan -- Rather than push the brute limits of process technology, Toshiba Corp. and Samsung Electronics are anxiously experimenting with novel device structures and manipulating current lithography tools to cheat the scaling limits imposed by today's floating-gate NAND.
Engineers at both companies offered glimpses into their efforts here last week at the VLSI Technology Symposium, where memory researchers made it clear that what's worked in the past won't work in the future. "To continue reducing the bit cost for future ultrahigh-density flash memories, some kind of solution other than shrinkage is necessary," said Toshiba's Hiroyasu Tanaka.
Toshiba is betting on its Bit Cost Scalable (BiCS) 3-D structure as a possible solution for low-cost, 20-nanometer-generation NAND. Samsung is turning to a new NAND structure as well as lithographic double patterning; it has already integrated multilevel NAND on 38-nm design rules to create an 8-Gbit memory test chip.
"For the below-40-nm generation, we have no [lithography] tool yet. With the combination of 193-nm ArF [argon fluoride] dry lithography and double-patterning technology, we tried to overcome the lithography limitation," said Donghwa Kwak of Samsung's semiconductor R&D center.
The team used self-aligned double patterning in three critical lithographic steps: active, gates and bit lines. Though the double-patterning process inevitably entails some overhead, the ability to downscale makes it worthwhile, Kwak said. Another key component used was twisted bit-line contact, to ensure isolation between adjacent bit lines.
Samsung said it was able to craft a memory cell measuring 0.076 micron x 0.078 micron. Performance was nearly on par with multilevel-cell NAND: Read access time measured 25 microseconds for transfer cycle and 30 ns for burst cycle, while block erase and program times measured 2 ms and 25 µs, respectively.
In the Samsung process, peripheral circuits are fabricated together with the first patterning of memory cells. The peripherals are built at the 60-nm generation; the second patterning creates 30-nm memory cells.
As the design rules shrink, floating-gate interference increases, making bits harder to read. To combat that problem, Samsung replaces the floating gate with a proprietary oxide-nitride-oxide layer that the company describes as charge trap flash. The so-called Tanos structure comprises tantalum (a metal), aluminum oxide (a high-k material), nitride, oxide and silicon layers.
Use of the Tanos structure marks the first application of a metal layer coupled with a high-k material in a NAND device. Samsung said the technique dramatically reduces cell-to-cell interference.
The team also introduced a "hemicylindrical" FET structure to improve the performance of the 30-nm-generation device. The subthreshold swing and off current were reported to be dramatically improved compared with those of planar cell structures. By combining the technologies, "we think that a 64-Gbit [30-nm] NAND flash memory will work successfully," Kwak said.
Samsung proposed using a 3-D structure for NAND memory late last year as a way to get around increasing bit costs. Now Toshiba has a 3-D structure of its own. Its BiCS technology uses a silicon-oxide-nitride-oxide-silicon (SONOS) memory structure that Tanaka said "is more cost-effective than a simple, stacked 3-D structure."