SAN JOSE, Calif. A standards group is moving forward with a draft specification aimed at solving one of the thorniest problems in signal integrity today—accurately modeling interconnects at 5 Gbits/second and higher. One vendor is already showing reference models based on the work from the I/O Buffer Information Specification (IBIS) group.
The so-called Bird application programming interface describes a method of using an executable file to query a high-speed interconnect without revealing proprietary information about the vendor's use of equalization. The API could be used with an EDA software tool, a hardware tester or a combination of the two.
To date, engineers have not had an accurate way to verify models of interconnects running at 5 Gbits/s or higher without obtaining full information from the vendor about its often patented techniques. Traditional tests often deliver closed eye diagrams when measuring chips at such speeds because they do not know how to accurately represent a vendor's proprietary equalization scheme.
Chip vendors typically supply software models of their parts, but they come in a wide variety of often incompatible formats. That makes it virtually impossible for OEM engineers to create accurate simulations of high-speed systems that use chips from multiple suppliers.
The issue has been particularly acute for engineers making high speed routers and switches. However, with the advent of a 5 Gbit/s PCI Express specification, the problem threatens to spread to a wider group of computer and peripheral makers.
The IBIS Advanced Technology Modeling task force has been working on the problem for more than two years. At a June 27 meeting the group agreed the draft of its Bird API was mature enough that it could be used to generate reference models. Signal Integrity Software Inc. (SiSoft; Maynard, Mass.) released the first of those models July 17.
"There are models up and running that can demonstrate modeling a million bits a minute," said Todd Westerhoff, a business development manager for SiSoft. "It takes tens of millions of bits to simulate a commercial equalization and clock-recovery scheme, so the performance is more than adequate," he added.
The IBIS group hopes to debug the API based on work building and using such models. If all proceeds smoothly, the task group could bring a final API up for approval to the overall IBIS group in September.
One wrinkle lies on the road ahead. A consultant involved in the work told EE Times that Agilent is working with a large chip maker, believed to be IBM, on an alternative approach. The two companies may present that approach at an upcoming IBIS meeting in China in September.
Engineers at Cadence Design Systems spearheaded the work on the current API which takes its name from the longstanding practice in IBIS of listing Buffer Issue Resolution Documents. Some of those documents date back to the early 1990s. Cadence demonstrated the approach working with a 6 Gbit/s serdes from IBM at DesignCon earlier this year.