WASHINGTON Xilinx Inc. said Tuesday (Aug. 14) it is collaborating with electronic design automation vendors to tackle FPGA design verification issues.
Xilinx (San Jose, Calif.) said in a statement that its engineers will work with counterparts at Cadence Design Systems Inc., Mentor Graphics Corp. and Synopsys Inc. "to define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today's 65-nm FPGAs."
Xilinx said it expects tools and methodologies developed over the next several months to be released in the first half of 2008.
"Verification has become a major, time-consuming portion of the FPGA design flow," Bruce Talley, vice president of the Design Software Division at Xilinx, said in a statement. "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65 nm and beyond."
Xilinx released its first 65-nm FPGA, the Virtex-5 platform, in May 2006.