Single-chip 16-Gbit MLC NAND flash devices from 50-nanometer-class processes were introduced in the first half of 2007. Adoption of MLC technology for NAND flash has been a crucial factor in achieving bit growth of NAND flash devices. As NAND flash manufacturers are tackling their next-generation process challenges with 40-nm-class technology for further scaling of flash cell size, efforts are being made to achieve more bits per flash cell with 4 bits per cell.
Spansion has already introduced its NROM-based MirrorBit Quad with its 90-nm process technology. It is expected that Spansion's next-generation 65-nm MirrorBit Quad products will be launched in the second half of 2008.
Implementing 4 bits/cell in NROM-based MirrorBit technology seems to be easier than doing so in floating-gate-based technology. Each of the two locations of NROM-based flash cell need to support 2 bits/cell, or four levels of different voltage levels. Floating-gate-based technology, however, should be able to distinguish among 16 voltage levels in each cell.
Although the challenge of writing and reading 16 voltage levels stored in the floating-gate-based flash cell seems daunting, Toshiba recently demonstrated the feasibility of doing so (Shibata et al., "A 70-nm 16-Gbit 16-level-cell NAND Flash Memory," 2007 Symposium on VLSI Circuits, pp. 190-191).
Even though MLC (2-bit/cell) technology has been a challenge for both flash manufacturers and flash controller vendors, supporting 4 bits/cell will be an even bigger challenge for them.
The distance between two read voltages is about 1.5 volts for an MLC flash device. But 4 bits/cell has only about 0.2 V to differentiate between two adjacent states. This is only 13 percent of the voltage distance of an MLC flash device.
This will inevitably increase the bit error rates of 4-bit/cell NAND flash devices. The error-correcting code (ECC) requirement for NAND flash devices, with the introduction of MLC technology and scaling, has been increased from a 4-bit ECC requirement at the 70-nm process node to an 8-bit/15-bit ECC requirement at 50 nm. For 4-bit/cell technology, this requirement would be even greater. For the Toshiba 70-nm 16-level-cell NAND flash, the increased ECC requirement and extended page size incur around 15 percent in chip-size overhead compared with the device's 2-bit/cell (or four-level-cell) counterpart.
Based on Semiconductor Insights' research, Toshiba's 70-nm 16LC (16-level-cell) 16-Gbit NAND flash device has a smaller die size than its 56-nm MLC 16-Gbit NAND flash device.
As a reference for 4-bit/cell chip size reduction, Spansion's 1-Gbit ORNAND devices manufactured in two different technologies (MirrorBit and MirrorBit Quad) are compared here. Note that the 4-bit/cell technology can reduce the chip size by 42 percent with the same process node.
The 4-bit/cell technology requires a greater number of programming pulses and read pulses to program and read. That will cause more signal coupling to the floating gates, thereby creating more disturbance noise. The program and read algorithm for 4-bit/cell technology should take the coupling noise issue into account for data integrity and performance.
The programming and reading of 16 voltage levels to and from the flash cell, combined with the increased ECC re- quirement, will affect the performance of 4-bit/cell NAND flash significantly. It has been reported that the programming performance will be degraded to a level closer to that for NOR flash devices (0.62 Mbyte/second).
Toshiba 56-nm 16-Gbit die. |
Given the relatively poor performance of raw NAND flash with 4 bits/cell, the role of the NAND flash controller to maintain application performance is expected to be even more important in the future.
Although this 16LC technology is based on the theoretical Gaussian model for the behavior of a multibit/cell NAND flash device, SanDisk seems to have figured out a better way of modeling the behavior. The x4 technology that has been in development for more than five years is a system solution with a special controller chip (x4 controller) and x4 software. The x4 controller chip has more than a million gates and uses sophisticated signal processing techniques to place cell states optimally to achieve 4 bits/cell.
The road to 4-bit/cell NAND
Toshiba has expressed its intention to have its "super multilevel cell" technology established and create the market for 3-bit/cell and 4-bit/cell technologies. The International Technology Roadmap for Semiconductors also modified its semiconductor road map in 2007 and added 3-bit/cell NAND flash technology as an interim solution between MLC and 4-bit/cell technology.
One key to achieving the continuous scaling of NAND flash cell is lithography. When companies are faced with the challenges of cell scaling, 3-bit/cell technology could be a candidate to continue the bit growth with reasonable effort.
These 3-bit/cell and 4-bit/cell technologies are expected to be in the market sometime between 2009 and 2011. Companies are also expected to try various 3-D stacking techniques to achieve more bits per chip before they make the transition to charge-trapped flash technology.
Spansion, in the meantime, has announced its plans for 65-nm MirrorBit Quad products in the second half of 2008. With Spansion's recent acquisition of Saifun, MirrorBit Quad development is expected to accelerate to address the growing demand in the data flash market.
In the next two to three years, the NAND flash industry is expected to make more-reliable and faster multibit/cell-based products. Programming and reading eight levels or 16 levels of small voltage differences from a smaller flash cell will be a challenge for manufacturers that will require innovative and creative approaches in the circuit design, layout and programming algorithms and in the ECC circuitry. Inherent degradation of programming performance should be properly addressed to maintain the application performance of flash devices. Collaborative efforts between flash device manufacturers and controller design companies will become more important for these products.
Special technologies, including a separate controller chip with a sophisticated software algorithm to enable 4-bit/ cell technology, are expected to play a significant role in the next few years. More components of flash performance are expected to migrate from the flash chip design to the controller or companion chips.
A highly optimized and sophisticated program and read algorithm will be one of a few critical elements of successful 3- bit/cell and 4-bit/cell flash product development. n
Young Choi (firstname.lastname@example.org) is lead memory analyst at Semiconductor Insights, a CMP company specializing in in-depth technical investigation of ICs and electronic systems.
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