BENGALURU, India Researchers at the Indian Institute of Technology (IIT) have come up with a new approach for test engineers to balance the need handling test data compression and power consumption parameters in large SoC designs.
Test engineers usually take a joint approach to handling test data compression and scan chain transition reduction. But these parameters frequently end up being tested separately. Rather than using a compromise method, the IIT researchers said their approach presents test engineers with the total available trade-off between compression ratio and scan-in power consumption in a dictionary-based test data compression scheme.
Engineers testing large SoC designs can then select a suitable point on the trade-off graph to satisfy their needs, the researchers claimed in a paper describing the results of research funded by India's Department of Science and Technology.
The new test method is timely given the need to integrate several IP cores in a SoC design. That presents system complexity challenges for test engineers, requiring them to use a power-efficient strategy while shortening test time. Using several cores means more test data. While more test data compression techniques have been developed, power minimization during testing remains an obstacle.
IIT's approach is based on a trade-off between compression and test power in dictionary-based test compression. While a large number of "don't cares" exist (previous approaches sometimes mapped them to "0"s or "1"s), the researchers coding scheme used for compression specified that these "don't cares" are handled in an efficient manner to achieve a high compression ratio.
"That coding scheme used in compression techniques may eventually increase the test power [but] it may not always be an advantage to use a powerful compression scheme if it increases test power significantly. It is necessary to look at the two aspects simultaneously and have some strategy which would give a balanced solution of test data compression and test power," they said.
The IIT researchers said power consumption while testing is directly proportional to switching activity, adding that a dictionary-based compression technique is necessary to reduce test data size and cut testing time.
"At the same time, such a technique would increase the flip count in a test vector set, thereby increasing test power" they added.
The researchers said their scheme "has a few limitations," including that "it does not compute the scan-out transitions."
Another problem is power leakage, which is expected to dominate future SoC designs. The IIT researchers said they need to incorporate a leakage model into their power calculations.