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Gate leakage, down and out?

12/4/2007 03:00 PM EST
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CYI
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re: Gate leakage, down and out?
CYI   12/4/2007 10:30:59 PM
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While it is true that high-k materials will virtually eliminate gate leakage, the use of these materials will not significantly reduce subthreshold leakage which will continue to account for a significant percentage of a chip's total power consumption. At 90nm, leakage power accounts for about 30% of a chip's total power and almost all of the leakage power is due to subthreshold leakage, as opposed to gate leakage. At 65nm, over 50% of a chip's power is due to leakage and about 60-70% is due to subthreshold leakage. At 45nm, gate leakage would have grown to overtake subthreshold leakage. With the use of high-k materials, the threat of gate leakage is tamed. However, subthreshold leakage will continue to be a critical parametric yield-limiting factor at 45nm and beyond.

donoman
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re: Gate leakage, down and out?
donoman   12/5/2007 6:21:13 PM
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CYI-what are you talking about? Being able to use a thinner EOT helps with gate control (short channel effects) as well as reducing gate leakage. Granted, this article is not impressive with an EOT of 390A but I suggest you don't mislead others with a lopsided view on gate dielectrics. Love, donoman

DBTI
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re: Gate leakage, down and out?
DBTI   12/5/2007 10:02:36 PM
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10A = 1nm. So 0.39nm = 3.9A, not 390A. This is impressive. If GOI is well controlled this could be a great solution. And I agree that a thinner EOT will improve sub-t leakage as well.

Phononscattering
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re: Gate leakage, down and out?
Phononscattering   12/5/2007 10:12:26 PM
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A leakage current of 1e-12 A/cm² is physically impossible with an insulator thickness of 2.4nm. It would required a material with an unrealistically high band gap. There appear to be factual mistakes in the article.

Phononscattering
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re: Gate leakage, down and out?
Phononscattering   12/5/2007 10:29:10 PM
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Also an EOT of 0.39nm with a dielectric thickness of 2.4nm requires an average dielectric constant of the gate stack of 25. This would require a crystalline dielectric without interfacial SiO2 layer. While this is not unheard of, it is typically not possible to achieve sufficient channel mobility in a gate stack like that.

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