SAN JOSE, Calif. The PCI Special Interest Group is making progress on a basket of feature extensions to its latest 2.0 specification, all of which should be available by June at the latest. The new features could enhance system performance as well as smooth a path for accelerators and storage devices riding the interconnect.
The enhancements include limited support for cache-coherent transactions as a way to synchronize traffic, particularly between host CPUs and co-processors, a new technique for handling virtual memory and support for multicasting. The SIG hopes to define these features—and perhaps others-- as engineering change notices on top of PCI Express version 2.0 by April, although some items may not be completed until June.
The work "has really come together these past couple of months. Training on the concepts has started to the members to prep them for the [spec] reviews," said one source who asked not to be named.
"It's all incremental advances, but in certain markets they will be significant," said a second source who asked not to be named.
Chip interconnects represent a competitive arena where Intel and archrival Advanced Micro Devices are sparring. Intel is expected to use the enhancements to Express as the main route for third-parties to link to its chip sets and CPUs, competing with versions of HyperTransport used by AMD.
The multicast capability will let a PCI Express switch blast one element of data to multiple end points, saving bandwidth and latency in some applications. The feature will be most useful in systems that use multiple graphics chips or monitors or systems with redundant or mirrored storage capabilities.
A number of the extensions bring some of the features of coherency to Express, creating a mainstream link between hosts and co-processors without all the complexity of a fully cache coherent interconnect. Although the SIG has not yet disclosed details yet, this appears to work by creating a coherency plane as a new abstraction level across which Express and a separate interconnect such as a processor bus can share information about transactions.
These new coherency-aware shared transactions can occur at the level of processors, chip sets and I/O devices. At the I/O level, these transactions can help plug a hole in virtual memory subsystems so that needed data can be retrieved quickly, reducing latency.
The PCI SIG actually forbids members to discuss details of proposals in progress. However, individual companies have publicly and privately disclosed parts of proposals they back.
For instance Intel, IBM and other partners disclosed some of the work last year under the name Geneseo. Advanced Micro Devices made a public presentation about its virtual memory proposal for I/O page fault handling at the Windows Hardware Engineering Conference early this year. In the end, the SIG will release work that has been developed and modified by a wide array of its members.
"Geneseo does not exist other than an Intel marketing term, and as a term it was never recognized by the PCI-SIG and is never used in any PCI-SIG discussions," said the first source. "All of the proposals have seen extensive discussion and modifications no matter the source of the proposal," he added.