WASHINGTON Intel Corp. researchers speaking at this week's International Electron Devices Meeting (IEDM) here described its 45-nm logic technology that for the first time incorporates high-k/metal gate transistors in a high-volume manufacturing process.
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) researchers also reported manufacturing gains at 32 nm.
Intel's transistors feature a high-k gate dielectric with an electrical oxide thickness of 1.0 nm along with dual-band edge metal gates and third-generation strained silicon. Intel claims the result is the highest drive currents yet reported for NMOS and PMOS devices. The technology relies on trench contact-based "localrouting," nine layers of copper interconnects with low-k ILD and 193-nm dry patterning lithography. Intel also stressed that its 45-nm devices use lead-free packaging.
Intel's process yield, performance and reliability were demonstrated on 153-Mb SRAM arrays with SRAM cell sizes of 0.346-micron2 used on multiple microprocessors.
In their presentation at IEDM, Intel researchers noted MOS devices' long dependence on silicon dioxide as the transistor gate insulator of choice. Electrical oxide thickness (TOX) has scaled to about 0.7x per generation up to 130 nm. But scaling has slowed at the 90- and 65-nm nodes as silicon oxide runs out of atoms and gate leakage power limits further scaling.
High-k gate dielectric materials have promised continued scaling at low gate leakage levels. Among the many challenges to deployment have been Vt pinning, mobility degradation due to soft optical phonons and poor reliability. These challenges remain in finding a compatible integration scheme that addresses thermal budget concerns, the researchers said. Intel claims to have overcome high-k/metal gate integration challenges, enabling a return to 0.7x TOX scaling while simultaneously reducing gate leakage by more than 25 fold.
A key challenge was simultaneously integrating high-k gate dielectrics, optimal "workfunction" metal gate electrodes and highly strained silicon channels. Transistors used 160-nm gate pitch, 35-nm physical gate length and hafnium-based 1.0-nm EOT high-k gate dielectric material.
Intel reported the first fully functional 45-nm 153-Mb SRAM in January 2006. Researchers here claimed that mature yields have been demonstrated and the technology is now in volume manufacturing.
TSMC also reported at IEDM a 32-nm low-power foundry technology integrating a 0.15-micron2, 6-T high-density SRAM using low-standby transistors, analog/RF functions and Cu/low-k interconnects for mobile SoC applications.
TSMC researchers claimed the device is the smallest functional 2-Mbit SRAM test chip at the 32-nm node. The foundry claims to have achieved ultra-high density SRAM cell patterning with 1.2 NA/193-nm immersion lithography using a double patterning approach. TSMC researchers said they achieved a resolution of 100-nm full pitch and 40-nm contact holes for all metal and plolysilicon layers.
TSMC further claimed theirs is a cost-effective 32-nm foundry technology featuring digital, analog/RF functions and dense memories.