Leading-edge foundries are just beginning to ramp their 45-nanometer processes, but vendors are already looking to the next challenge--perhaps their biggest to date: the race to develop and ship high-k dielectrics and metal gates for the 32-nm node.
High-k and metal gates are key building blocks for scaling and enabling the next-generation transistor. But the technologies' complexity raises questions about whether foundries can ramp production with high-k materials and metal gates in a timely and cost-effective manner.
Complicating matters, the movement to high-k/metal gate has split into factions that variously embrace gate-first, replacement-gate and hybrid approaches. Chip makers must hope they bet on the right foundry technology in a complex arena where no clear winners have yet emerged.
IBM Corp. and its joint development partners--Advanced Micro Devices, Chartered Semiconductor Manufacturing, Freescale Semiconductor, Infineon and Samsung--have not formally announced their 32-nm process. But at last week's International Electron Devices Meeting (IEDM) in Washington, IBM disclosed that it had devised a high-k gate-first technology for the node. The technology will be available to IBM and its alliance partners--including foundry members Chartered and Samsung--in the second half of 2009.
Rival foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. is quietly readying its own high-k/metal gate technology but has not announced a timetable for release. TSMC has said its general 32-nm process is slated for "risk production" by the third or fourth quarter of 2009.
Other leading-edge foundries, including Fujitsu, Semiconductor International Manufacturing Corp. (SMIC), Toshiba and United Microelectronics Corp. (UMC), are separately developing high-k/metal-gate solutions.
But with the foundries' hands full ramping their complex 45-nm processes, do they have what it takes to bring high-k and metal-gate technologies into production at 32 nm? High-k development is complex, costly and difficult. At the 32-nm node, overall process-development costs could hit $3 billion--twice the cost seen at 65 nm, according to Gartner Inc.
Thus far, only Intel Corp. and NEC Electronics Inc. have announced they are shipping logic devices equipped with high-k materials. Intel is shipping processors based on high-k and metal gates at the 45-nm node. NEC has delivered ASICs based on high-k at 55 nm.
"The challenges for a foundry to develop high-k are the same as for an IDM," said Dean Freeman, an analyst at Gartner (Stamford, Conn.) "They need to develop a transistor process that integrates the high-k [dielectric with the] metal-gate stack. The challenge is to integrate the process correctly."
The separate PMOS and NMOS materials must be integrated into a scaled CMOS device. And there are fundamental side-effects in moving to high-k, notably threshold voltage pinning, which can impair performance.
Perhaps a larger question than who can bring high-k/metal gates to market is who requires them. The technology is ideal for wireless devices, where low-standby power is required. But "many consumer applications will not need high-k and metal gates," Freeman said. "This is due in part to cost."
"Based on input from our customers, the demand for high-k materials only arises when working with process technologies below 32 nm. At larger process nodes, the benefits of using high-k materials are unclear, so therefore we have not experienced any customer demand," said Rakesh Sethi, director of business development for the Custom SoC and Foundry Business Unit at Toshiba America Electronic Components Inc. (Irvine, Calif.).
High-k is not a new technology; DRAM vendors have used it for some time to reduce capacitor size in shrinking memory designs. What's new is the use of high-k dielectrics and metal gates as enablers of leading-edge logic.
For decades, logic IC makers have used silicon dioxide as the key insulator for the transistor gate dielectric, while deploying polysilicon to form the gate electrodes for both the NMOS and PMOS transistors. That combination worked until the 90-nm node, when the industry could no longer scale the SiO2 gate dielectric. That, in turn, caused leakage and power consumption to soar.
To combat the problem at the 90-, 65- and 45-nm nodes, most chip makers have devised strain engineering techniques that have forestalled the need to change the gate dielectric or electrode materials. Beyond 45 nm, high-k materials are expected to replace SiO2, while metal gates are targeted to displace the polysilicon-enabled electrode. High-k is based on hafnium materials that are not compatible with polysilicon.
Some companies are ahead of the curve. Intel is shipping 45-nm processors that use a replacement-gate approach, as opposed to the gate-first technology used by IBM. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.
Last January, IBM and its technology partners announced a high-k/metal gate technology for the 45-nm node. IBM described the technology as a "proprietary" approach geared for undisclosed products in the 2008 time frame.
There has been speculation that IBM is having integration problems with the PMOS portion of the technology and that the problems are delaying the process for its partners. But in a recent interview, Gary Patton, vice president of IBM's Semiconductor Research and Development Center, said the company's high-k technology is on track.
IBM has yet to roll out high-k in a product. One IBM partner, AMD, desperately requires high-k at 45 nm to keep up with Intel. But in a move that raises questions about the readiness of IBM's technology, AMD said it has yet to make a commitment to use high-k at 45 nm, saying instead that the dielectric shift is an "option" at that node.
AMD (Sunnyvale, Calif.) will include high-k/metal-gate technology in its 32-nm products, said John Pellerin, AMD's director of logic technology development and project leader on a joint development effort with IBM. AMD expects to begin production of its 32-nm high-k chips sometime in 2010.
IBM and its partners claim to have developed a low-power foundry CMOS technology using the high-k gate-first approach and have demonstrated 32-nm SRAMs, with cell sizes below 0.15 micron2, that are the first working 32-nm parts to use the gate-first high-k approach.
The characteristics of the high-k material reduce total chip power consumption by as much as a 45 percent compared with the technology used at 45 nm, a critical factor for achieving longer battery life in handhelds, IBM said.
TSMC, for its part, "has been working with IMEC [the Interuniversity Microelectronics Center; Leuven, Belgium] on high-k and metal gates, as well as with their partners, such as TI, for several years," said Gartner's Freeman.
TSMC "appears to be capable of releasing a high-k/metal gate process in the second generation of its 45-nm node in late 2008 or early 2009," Freeman said.
A more likely scenario is that TSMC will offer the technology at the 32-nm node in the second half of 2009. Last week, TSMC tipped its hand as part of an IEDM announcement from IMEC, which reported progress in improving the performance of CMOS using hafnium-based, high-k dielectrics and tantalum-carbide metal gates targeting the 32-nm node.
A major challenge in using high-k dielectrics for CMOS devices is the high threshold voltage, resulting in low performance. But IMEC claims to have developed a simple, lower-cost integration scheme using only one dielectric stack and one metal. A thin dielectric cap is deposited between the gate dielectric and metal gate, modulating the work function toward the optimal operating zone, according to IMEC. Both a lanthanum- and a dysprosium-based capping layer were used for NMOS, with an aluminum-based capping layer used for PMOS. With the technology, IMEC's partners TSMC and NXP were able to demonstrate what the companies said was an "excellent drive current" specification.