PORTLAND, Ore. Nanochip Inc. (Fremont, Calif.) claims to be on-track to the development of terabyte memory chips that combine phase-change media to cantilever read/write heads controlled by a microelectro-mechanical system (MEMS).
The memory chips will use conventional, DRAM-like interfaces, but internally will function like a multiple-head hard drive, where slaved MEMS cantilevers will move in unison over their array of bit cells to read and write phase-change media. Nanochip claims its first prototypes will be delivered in 2009, with volume production scheduled to 2010.
"We are well on-track to meet our original schedule of reaching full commercialization of our first product offering by 2010," said Gordon Knight, CEO of Nanochip.'
Nanochip's potential bit cell size measures 2 by 3 nanometers, accounting for its terabyte-per-chip goal. Initial prototypes will have bit cells measuring about 15-by-15 nanometers for capacities around 100 Gbytes per chip in 2010.
The company estimates it will be able to double capacity every year thereafter without scaling down the relaxed 1-micron geometry of their process. Instead, it will seek to improve the media and refining control of the ganged MEMS cantilever read/write heads.
"Nanochip's technology is well positioned to provide memory capacity with exponentially higher storage densities at a cost per gigabyte significantly below that of flash technology," said Keith Larson, vice president and director of manufacturing, memory and digital health at Intel Capital.'
Nanochip recently finalized its latest round of funding, including $14 million from venture capitalist that include Intel Capitol and JK&B Capital. Founded in 1998, Nanochip's previous funding rounds included $10 million in 2006. It counts Microsoft Corp. among its backers.
Nanochip holds seven U.S. patents, and has applied for 34 more. The company licensed its phase-change media from Ovonyx (Rochester Hills, Mich.)