SAN JOSE, Calif. Seeking to solve a major bottleneck in chip designs at the 32-nm node and beyond, Brion Technologies Inc. is rolling out a one-two punch in the arena: The company is debuting its latest hardware accelerator and a separate double-pattering solution.
The first product from Brion (Santa Clara, Calif.) is Tachyon 2.5, a standalone, hardware-assisted optical proximity correction (OPC) verification accelerator that is aimed for 32- and 22-nm designs and is said to be 2.5 times faster than the company's previous system.
The second product, Tachyon DPT, is a solution that runs on the company's Tachyon hardware accelertors.The technology is aimed for the inevitable shift towards double-patterning lithography in advanced chip designs at the 32-node and below. It makes use of a model-based approach throughout the flow that is said to reduce overall cycle times in OPC verfication.
Brion, a subsidiary of ASML Holding NV of the Netherlands, said the new products fall into what the company calls computational lithography. The solutions allow chip makers to meet the low k1 requirements for memory and logic devices at the 32-nm node and below.
The products continue to put lithography-equipment giant ASML on a collision course with EDA vendors Mentor Graphics Corp. and Synopsys Inc., two large providers of OPC software.
But all vendors are scrambling to solve a major problem in the design flow. At 90 nm and below, OPC must be run on every chip before production. But OPC is one of the most computationally demanding parts of the entire IC design-to-manufacturing cycle. "It is putting a strain on the computation side" of the equation, said Neal Callan, Brion's vice president of product operations.
Last year, Mentor Graphics announced a deal with Mercury Computer Systems to provide a hardware-accelerated platform for OPC, based on the Cell processor. Now, Brion is increasing the stakes by rolling out Tachyon 2.5, build around x86-based, quad-core microprocessors. Brion claims it has the option to use quad-core processors from Advanced Micro Devices Inc. and Intel Corp.
There is more to the new Tachyon 2.5 product than just a mere "straight CPU swap," Callan said. The previous-generation hardware accelerator with a "CPU swap" could speed up the machine by a factor of 1.5 to 1.7. With the addition of new co-processing and monitoring technology, the new system is 2.5 times faster than previous accelerators from the company, he said.
Like the previous hardware, the new system supports up to 256 kernals for optical modeling. It has up to an 8 micron diameter optical interaction range for the 45-nm node and up to 7 micron diameter range for the 32- and 22-nm nodes, according to Brion.
Meanwhile, Brion's second solution, Tachyon DPT, enables chip makers to move into the double-patterning era. The solution, along with Brion's Tachyon Double Dipole Lithography (DDL) technology, uses a model-based approach in double-patterning applications.
"Double patterning is a semiconductor exposure method that involves splitting dense circuit patterns into two separate, less dense circuit patterns that are then printed individually on a target wafer," according to Brion. "The second pattern is printed between the lines of the first pattern, enabling the fabrication of denser patterns than would otherwise be possible. This technique is helping to extend current microlithography technology to future production nodes."
DDL supports generic double-patterning lithography. DPT supports two double-patterning techniques in OPC verification: litho- (litho-etch-litho-etch) and spacer-DPT. Tachyon DPT offers full-chip conflict-free pattern split, model-based OPC, model-based stitching compensation and automatic density balancing.
Tachyon DPT is currently available and Tachyon 2.5 will be available during the second half of 2008.