SAN JOSE, Calif. Cisco Systems debuts Tuesday (March 4) a router that packs on a custom 40-core processor a wide variety of networking services. The Ethernet giant aims to leverage its expertise designing complex ASICs to leapfrog competition in the $5 billion market for edge routers.
The Quantum Flow Processor takes to a new level Cisco's work on ASICs for its networking systems, surpassing in some ways technology in mainstream server CPUs from Intel Corp. and Sun Microsystems. Analysts said the move is a savvy one for Cisco, although some complained the company is keeping details of its new chip sketchy.
Cisco claims it spent $250 million and five years developing its Aggregation Services Router 1000, $100 million of that just on the flow processor. The router handles at rates up to 20 Gbits/second functions including firewall, IPSec virtual private networking, deep-packet inspection and session border control.
"There are half a dozen or so appliances all being used to provide these functions at the edge of carrier and end-user networks," said Pankaj Patel, general manager of Cisco's service provider group. "Our value proposition is to put them in one small form factor box to reduce capital and operating expenses," he added.
Competitors such as Juniper Networks and Redback Networks—and Cisco's existing 7600 series routers—typically slot multiple cards in a chassis or stack appliances in a rack to handle all the features increasingly being processed on the network edge, said Eve Griliches, a telecom analyst at International Data Corp.
"The more integrated you get it, the better performance you get when you are trying to run all the services at once, and eventually users will want to run all these services at once," Griliches said.
Key to the system is the 1.3 billion transistor flow processor, an 80W chip made in a 90nm process at Texas Instruments and designed using Cisco's customer-owned tooling. Each of its 40 Tensilica cores can handle up to four threads, far beyond the raw thread-level parallelism of Sun's 65nm Niagara or Intel's 45nm Penryn server CPUs.
"We looked outside and internally to see if there as anything we could use but nothing came close," said Nikhil Jayaram, director of engineering in Cisco's mid-range routing group. "Other architectures were about packet processing, but we wanted to do flow processing of stateful traffic," he added
"Multi-core processors and complex aggregation routers are converging in a way that means that the most complex communication processing chips now dwell at the edge of the public network," said Loring Wirbel, director of the EE Times Market Intelligence Unit. "The center of the network now means big, dumb, high-speed bit-pushing, while all the smarts reside at the edge of the public network, and core routers like Cisco's CRS-1 are no longer the premier platforms for high-performance network processors," he added.