Other approaches for evaluating processors for applications take a simulation/execution-based approach in which the application task is compiled for the target processor and executed either on an evaluation platform or simulated via a cycle-accurate simulator. In the alternative analytical approach, the application is neither simulated nor executed but is instead analyzed in light of the processor's instruction set architecture.
The IIT team assumed there to be many customized embedded processors differing in the instruction set architectures as architectural design alternatives. "We identify a base processor configuration which consists of instructions doing basic arithmetic, logical, comparison and jump instructions. Our goal is to evaluate the performance of the given application or application tasks on these different customized steps.
As the first step, execution time statistics of the application or each of the application tasks is obtained through cycle accurate simulation using the simulator for the base processor core. This is the only simulation run used in the new approach proposed and the execution time statistics obtained by this initial simulation run forms the input to the second step, where an evaluation engine predicts the execution time statistics for each of the customized embedded processors.
The inputs to the evaluation engine are the performance statistics got from the simulation on the identified base processor and a parameter file which captures the architectural differences in terms of the instruction set of the customized processor core in comparison with the identified base processor.
This file has the definition of all extra instructions contained in a customized processor. An instruction definition consists of the number of input/output parameters, latency information and dependency relations. Essentially, the evaluation engine tries to estimate how these architectural differences will effect the execution time of the application or application tasks.
We have presented a novel hybrid approach consisting of one time simulation of the application on an identified base processor architecture and then prediction of execution time on a customized processor by our evaluation engine. Along with the prediction of execution time, the application tasks are automatically augmented with CIs optimally for execution in the heterogeneous processors. Our approach also finds use in the application to architecture mapping during MPSoC design. Our work basically turns around the classic instruction selection problem for code generation. However, the presented framework is significant in the context of performance estimation for a given processor architecture and corresponding code-generation.
The evaluation engine in the new method proposed can only predict the execution time for a custom processor and refinements for improving the prediction accuracy is a natural extension to the present work. Interesting work in the future can be in augmenting the evaluation engine with cache performance estimation due to CIs and [the] effect of other micro-architectural parameters," they concluded.