SAN JOSE, Calif. Efforts to improve techniques for programming and measuring multicore processors take three small steps forward as the annual MultiCore Expo opens its doors this week (April 1-3).
The Multicore Association will announce it has completed work on a standard applications programming interface for communications and started work to define a standard for embedded virtualization. A related group will show the first fruits of its efforts to define a benchmark for multicore CPUs.
Polycore Software (Foster City, Calif.) will demonstrate at the Expo a working version of the new multicore communications API in one of its tools. The API aims to provide a standard way to link and synchronize different kinds of cores in a processor.
"The demo itself may not be very sexy, but it's fully functional and we're starting to get some traction," said Markus Levy, president of the Multicore Association.
Several companies helped define the API including Freescale, Imperas, Intel, MIPS, Texas Instruments and Tilera. However, none have publically committed to using it yet.
Separately the association is officially kicking off work on setting a standard for hypervisors that control how embedded processors virtualize hardware resources. The group is initially trying to define what areas are ripe for standards in the area, focusing on issues such as on-chip communications and debugging.
"There are more companies interested in the hypervisor issues than I expected," said Levy. "The processor guys are really into and the whole effort that was kicked off by Nokia Siemens Networks," he added.
Finally the Embedded Microprocessor Benchmark Consortium will show the first results of a new multicore processor benchmark it developed run on a variety of processors with two to 16 cores. However, EEMBC will not identify the names of chips it measured, something it leaves to the chip vendors.
One demo will show very different results from the same workload run over two different dual-core processors. Other demos will show how some workloads scale linearly and others do not scale at all when run on the same multicore chip.
"This is some of the most interesting benchmark data I have seen because very complex," said Levy who is also president of EEMBC. "You are dealing with systems-level issues such as OS scheduling techniques, context switching and varying peripheral sets," he said.
"The point right now is that to understand multicore performance you have to look at a lot of different things," he added.
A host of benchmarks are currently in use for multicore chips ranging from Dhrystone Mips on set-top boxes and Specmarks to Java user interface metrics, said Jack Browne, vice president of marketing at MIPS Technologies. "Everybody is still struggling to determine what the right benchmarks are," Browne said.
The synthetic benchmarks are not as useful as those based on real-world applications. However, system makers are reluctant to release their applications code for open testing, Browne noted.
EEMBC has released the benchmarks to one user to get feedback. It will decide the terms for licensing its new benchmarks in a meeting in mid-April.
Systems makers are particularly interested in the new metrics, said Levy.
"Some of the telecoms OEMs are really struggling because they are finding in the shift from using two single-core chips to one multicore chip performance is going down. That's because they now have to share resources like caches," he said.