SANTA CLARA, Calif. Through new research, standards and tools, the industry is just starting to address what's being called a software gap between a rising tide of multicore processors and a lack of parallel programming tools and techniques to make use of them.
The gap came into stark focus in the embedded world at the Multicore Expo here this week, where chip makers Freescale, Intel and MIPS and a handful of silicon startups sketched out directions for their multicore products. Others warned that the industry has its work cut out for it delivering the software that will harness the next-generation chips.
"There is a major gap between the hardware and the software," said Eric Heikkila, director of embedded hardware research at Venture Development Corp. (VDC; Natick, Mass.).
About 55 percent of embedded system developers surveyed by VDC said they are using or will use multicore processors in the next 12 months. That fact is fueling the company's projections that the market for embedded multicore processors will grow from about $372 million in 2007 to $2.47 billion in 2011.
In the PC market, the figures are even more dramatic. About 40 percent of all processors Intel shipped in 2007 used multiple cores, but that will rise to 95 percent in 2011, said Doug Davis, general manager of Intel's embedded group.
But on the software side, vendors reported that only about 6 percent of their tools were ready for parallel chips in 2007, a figure that will only rise to 40 percent in 2011, VDC said. As much as 85 percent of all embedded programming is now done in C or C++, languages that are "difficult to optimize for multicore," said Heikkila.
"There's a need for a short-term fix to make C/C++ more expressive, as well as a long-term solution with new languages and tools," he said.
Changing techniques could be as hard as developing new tools, according to Alan Gatherer, chief technology officer of the communications infrastructure group at Texas Instruments. "We are dealing with legacy methodologies as much as legacy code," he said.
"If you go to companies such as Ericsson, they have hundreds of programmers writing code in very disciplined ways. So a lot of new software ideas are going to have to prove themselves, because you can't turn an oil tanker on a dime," said Gatherer.
Michael McCool, chief scientist of startup RapidMind, called for a new programming model to help developers better understand how to optimize their applications for parallel chips. Such a model would need to automate as much as possible while giving users override options and drill-down mechanisms, McCool said.
"Complexity [in multicore programming] explodes beyond a certain point, and that point is fairly low," he said.
The fundamental issues behind creating a mainstream parallel programming model are just starting to come to light. "I think we are beginning to see where the heads of the monsters are," said Wen-mei Hwu, a veteran researcher in parallel programming and professor of engineering at the University of Illinois at Urbana-Champaign.
The university recently won a $10 million grant from Intel and Microsoft to explore new parallel programming techniques. "There is really only room for one model of parallel programming. No one can afford to write applications in multiple models," said Hwu.
As co-chair of the university's new parallel research center, Hwu said he wants to build programming frameworks to limit variables such as dependencies in parallel software that create thorny problems for compilers. "We believe the frameworks should also serve as a source of information available to the compilers and underlying hardware," he said.
The university will partner with another center funded by Microsoft and Intel at the University of California at Berkeley. "It's not a competitive situation," said Hwu.
Separately, Illinois researchers are seeking $10 million to create a next-generation parallel processor. Called Rigel, the chip aims to anticipate future many-core processors by extrapolating directions in today's general-purpose multicore computer and graphics chips.
Sanjay Patel, who designed the physics processor from startup Ageia Technologies (recently acquired by Nvidia), will lead the chip design. Hwu will lead work on applications for the chip in areas such as video surveillance. The team has set an ambitious goal of defining a range of chips from a 1-watt Teraflops processor to a 100-W 10-Tflops CPU.
In terms of standards, the Multicore Association announced at the Expo it has completed work on an applications programming interface for communications between cores, and is now working to define a standard for embedded virtualization.