The decision to move to a new semiconductor process node is a difficult one involving complex trade-offs and uncertainties, particularly at advanced geometries like 45 nanometers. For designers, two key considerations loom large: achieving the target product specifications in terms of performance and unit cost, and hitting product introduction windows within a budgeted amount of design resources (manpower, EDA tools and mask costs).
At 45 nm, trade-offs between leakage and performance (frequency) drive the choice of both process technology "flavor" (low power vs. performance driven, for example) and design methodology, in terms of the area overhead required to incorporate leakage-mitigation schemes and their associated circuitry in the design. In terms of unit cost, a designer must factor in what die size is achievable and the expected yield at the time the device will ramp to volume.
At advanced nodes, yield is driven increasingly by systematic issues rather than random or pure defect-related yield. Systematic yield in this context is characterized by factors influenced by the design, not pure manufacturing-related causes. Yield loss can be both catastrophic (nonfunctional) and parametric (not meeting required specifications). At previous nodes, yield has been the purview of fab engineers. But at 45 nm, time and resources must be devoted to yield on the design side.
Variability is at the root of this disturbing trend, in terms of shape distortion due to printing complex shapes with low-k1 lithography. This manifests itself in both catastrophic failures--hot spots resulting in opens or shorts--and in device variability impacting parametric yield to either frequency or leakage (power) specifications.
To date, designers have dealt with these issues in two main ways: by iteratively postprocessing designs in an attempt to mitigate hot spots, and by margining the design to address device variability. Both of these approaches affect design costs, time-to-market and the ability to extract the price/performance advantage from a new node, diminishing the appeal of a 45-nm move.
In addition, there lurks an evil cousin of variability called context-dependent variability that, unfortunately, doesn't raise its ugly head until actual silicon is tested. Context-dependent variation is associated with the distortion of printed shapes based on what shapes are placed adjacent to them in the final construction of the chip. Because feature sizes at 45 nm are now so much smaller than the wavelength of light being used to print them, the neighborhood of interaction associated with context-dependent variability has expanded, making postlayout analysis of these interactions impractical from the standpoint of time and compute resources.
A new approach to dealing with variation is to address it at the source, producing competitive layouts for logic (in terms of area) by utilizing straight-line patterns on a deterministic grid. The assembly of logic blocks using standard cells designed in this manner has reduced leakage associated with gate length critical-dimension variation by 2.5x, and virtually eliminated context-dependent variation by creating a uniform and predictable environment at a block level.
On the manufacturing side, moving to 45 nm involves making a multibillion-dollar investment in equipment. For pure-play foundries, it represents the ultimate Field of Dreams, "build it and they will come," gamble if the above considerations are not addressed. The trend of foundries investing in design infrastructure, reference flows and physical intellectual property is evidence of this gamble. Achieving the optimal result, however, will require more co-optimization of design, particularly physical design and IC-manufacturing process development.
Clear evidence of this new reality is Intel's decision to remain on dry lithography rather than switch to immersion scanners at 45 nm, while also restricting its design approach to straight-line shapes to achieve a more-optimal result. Immersion lithography systems can cost as much as 47 percent more that dry systems. A design solution that can extend the life of capital assets will be a critical tool to continue to exploit the economic premise of Moore's Law.
Continued use of random, two-dimensional layouts is making design rules unmanageable and preventing design/process co-optimization. But placing restrictions on designers without delivering a comprehensive solution to achieving their design objectives only increases their burdens and slows the adoption of new technology nodes like 45 nm. This is why some designers object to the concept of restricted design rules.
A more-comprehensive approach that relies on gridded, unidirectional structures could be a key to unlocking the full use of expensive capital equipment and freeing designers from the vicissitudes of variability.
Neal Carney (email@example.com) is Vice President of Marketing at Tela Innovations. He has more 25 years of experience in the semiconductor industry most recently as vice president of marketing for ARM and Artisan Components. Carney received his B.S. degree in Physics and his M.B.A from Rensselaer Polytechnic Institute.