SAN JOSE, Calif. -- Virage Logic Corp. has rolled out its latest DRAM physical layer interface (PHY) solution, based on a 65-nm process.
The IP, dubbed the Intelli DDR2/3 PHY+DLL, is an ''all-digital'' solution aimed at ASIC and system-on-chip (SoC) designs in DDR memory interface applications.
Applications include video, graphics, portable electronics and others.
Supporting speeds of up to 1066-Mbps in a 65-nm process, the IP ''achieves performance and resolution levels that were previously only possible with analog solutions,'' according to Virage (Fremont, Calif.). ''Unlike all-digital solutions, analog solutions mandate costly silicon validation, with potential silicon re-spins, and therefore typically translate into longer time-to-market.''
"The Intelli DDR2/3 PHY+DLL not only delivers very high resolutions with an all-digital implementation, but it also provides a significant time-to-market advantage because its standard-cell architecture enables easy design portability across different foundries,'' said Kamalesh Ruparel, vice president and general manager of Virage Logic's application specific IP (ASIP) business.
The Intelli DDR controller and PHY+DLL support single data rate JEDEC standard SDRAM and Mobile SDRAM, double data rate JEDEC standard DDR1/2, DDR2/3, and MobileDDR as well as various multi-protocols.
The Intelli DDR2/3 PHY+DLL for the 65-nm G process is available now with pricing starting at $180,000.