BURLINGAME, Calif. -- Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on through-silicon vias (TSVs)--continues to generate steam.
In fact, TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.
Is TSV all hype or a reality? The industry has been talking about TSV technology for years, but there are few products to show for it. One of the few TSV-based products in the market is a CMOS image sensor from Toshiba Corp. Other TSV devices are being demonstrated by IBM and the large memory houses.
There are a range of complex and competing technologies in the arena, many of which are unproven and costly. On the manufacturing front, there are a handful of proposals: chip-to-wafer, wafer-to-wafer, TSV first, TSV last and even self assembly. There are also a number of competing material schemes: copper-to-copper, gold-to-gold, solder and others.
Each methodology, which has various trade-offs, could eventually find a place in the commercial market, said Michael Shapiro, senior technical staff member in the Systems and Technology Group at IBM Corp. "It may be application specific," Shapiro told EE Times at IITC. "It depends on what you're going to do."
The question is whether TSV-based technology will enter the mainstream or remain a niche. "I think it's a going to be mainstream," he said.
"We're already seeing it in CMOS image sensors," said Dean Freeman, an analyst with Gartner Inc. "The memory guys are looking very hard at it."
Chip scaling will continue for some time, but the costs are becoming enormous. So, some chip makers are looking at devising 3D devices using ICs with current-generation geometries. The devices are then connected using tiny and multiple TSVs.
The need for 3-D interconnects and packages has become more critical amid what some call a looming interconnect crisis experts believe could emerge by 2009. The crisis stems from the fact that chip scaling is shrinking the aluminum or copper interconnects in chip designs, causing potential timing delays and unwanted copper resistance.