Other EDA vendors sell different schematic-layout packages, bolted on top of the proprietary p-cell libraries for analog design. These tools and Cadence's do not interoperate. To read the data from one tool to another, designers must use so-called translators, which sometimes cause errors in the design flow, said Tom Quan, deputy director of design services marketing at TSMC.
That's not the only headache in analog. TSMC, for one, generated and maintained 2,500 new and different PDKs in 2007. A PDK consists of several basic elements in the analog/custom IC flow: schematic symbols and component distributed formats; p-cell libraries; Spice models; and technical files.
Each PDK is geared for a particular customer or design, but each kit is also incompatible with the others--and expensive.
Taking a step toward interoperable p-cell libraries that can be used with any OpenAccess-based IC layout tool, five EDA vendors last year formed the IPL alliance. They were Applied Wave Research, Ciranova, Silicon Navigator, SpringSoft and Synopsys. Others have since joined, including Helic, Jedat, Magma, Mentor, Micro Magic, Virage and, now, TSMC.
The alliance built its open-source, interoperable p-cell library upon Ciranova's PyCell Studio, a free tool that generates PyCells, or "universal" OpenAccess-based p-cells, based on a programming language called Python. PyCell Studio competes with Cadence's technology.
Late last year, the alliance expanded its charter to the development of a "standard" PDK that will operate over the Open- Access database. Ed Lechner, director of product marketing at Synopsys and chairman of IPL, said the group has demonstrated a proof-of-concept PDK. There are reportedly no bugs with EDA tools that support the OpenAccess database. There are some issues with Magma's tools, which do not directly read OpenAccess, sources said.
Magma denied those reports in regards to its analog EDA tools, dubbed Titan. ''Magma's Titan platform directly reads and writes OpenAccess and does not have any known issues directly reading or writing OpenAcess,'' said Ashutosh Mauskar, vice president of product and business development of the Custom Design Business Unit at Magma.
The alliance claims to have tested the proof-of-concept library with Cadence's latest Virtuoso 6.1 tool. Nevertheless, it doesn't appear that Cadence will join the group. "I don't see it as a revolutionary step," said Steve Lewis, director of product marketing at Cadence. "We're not sure what the customer will derive from it."
Cadence, however, does see the value of interoperable PDKs. "Industry interoperability is a good thing," Lewis said. "For TSMC, I'm sure it's a noble cause," because "they have to do a lot of PDK development."
With regard to analog, the EDA giant is not standing still. Cadence has released a new version of Virtuoso that extends the technology for mixed-signal designs down to the 45-nm node.
Onslaught of tools
Clearly, Cadence will get a run for its money. At DAC, Synopsys was quietly showing its new, automated analog layout tool, code-named Orion. The week before, Ciranova unveiled Helix, an automated analog layout solution. Helix's primary inputs are a Spice netlist and a PDK containing either Cadence's Skill-based p-cells or Ciranova's PyCells. The output is full device-level placement in either OpenAccess or a GDS format.
"Analog and mixed-signal design is the last major EDA market not served by automated layout methods," said Eric Filseth, Ciranova's CEO. "Up to now, the tools simply haven't delivered results acceptable to analog engineers. Helix builds on our proven PyCell technology to enable large and practical productivity gains at the full-circuit level."
Elsewhere, Helic SA launched a bond wire layout and inductance-modeling tool called VeloceWired. The tool is said to be suitable for use in the design of analog and mixed-signal ICs, where wire bond inductance may need to be considered as part of the overall component performance.
French EDA startup Infiniscale SA recently unveiled the TechYielder, for yield optimization of complex analog, advanced mixed-signal and RF blocks designed with sub-90-nm design kits. n