SAN JOSE, Calif. -- At the 2008 Symposium on VLSI Technology in Hawaii this week, Intel Corp. is expected to revisit its research on floating-body cells (FBCs) for advanced cache designs in microprocessors.
The big question is whether Intel is finally endorsing silicon-on-insulator (SOI) technology, as the company will describe the world's smallest FBC-based planar device on SOI for possible use at the 15-nm node. In related paper, Intel is also expected to describe new adaptive circuit techniques for SRAM cache cells. Both technologies are in R&D and still in the lab, it was noted.
Waiting in the wings in the race towards FBCs--or sometimes called floating-body RAMs (FB-RAMs)--is rival Advanced Micro Devices Inc. (AMD). Two years ago, AMD licensed an embedded FBC technology from Innovative Silicon Inc. (ISI).
For years, FBC has been touted as an alternative to conventional cache memory, because current capacitor-based technology is running out of gas. FBC is a candidate for increased memory density, compared to the standard six transistor (6T) cache memory that is used on all microprocessors today.
''In a standard DRAM, there is a capacitor and a transistor,'' according to ISI. ''The capacitor stores the logic state, 1 or 0, and the transistor provides the rest of the circuitry access to the capacitor. To read a DRAM memory cell, the transistor is turned on and the charge on the capacitor is allowed to flow onto a bitline, creating a small voltage which can then be detected.''
Jeff Lewis, vice president of marketing at ISI (Santa Clara, Calif.), warned that there are some major issues cropping up with the capacitor in DRAMs, prompting the need for a new architecture. ''Capacitor scaling is becoming almost impossible," Lewis said in a recent interview at the Design Automation Conference (DAC) in Anaheim, Calif.
Lewis speculated that there are possibly "one or two generations left in DRAM scaling,'' which may require the need for an FBC in memory designs. But he also noted there are some issues with FBC technology. "Bringing in a new memory technology is a challenge," he said.
In general terms, FB-RAM does away with the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is "floating" in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.
FBC technology enables three to four times the bits, compared to traditional embedded memory in cache designs, said Mike Mayberry, vice president of the Technology and Manufacturing Group at Intel (Santa Clara, Calif.) and director of components research.
This in turn speeds up computational rates, Mayberry said during a conference call. In 2006, Intel discussed a dual-gate transistor architecture for research purposes, which made use of FBC technology.
Now, at VLSI, the chip giant will describe a planar architecture using SOI, which is somewhat of a reversal from its previous stance. Unlike rivals AMD and IBM--which use SOI in processor designs--Intel has dismissed the need to use the technology in mainstream production.
Intel, not surprisingly, is taking a different approach than its rivals on the SOI front. ''The FBC is a planar device on SOI, but the film thicknesses are very different than what is considered conventional SOI,'' according to Intel.