PORTLAND, Ore. The Intimate Memory Interconnect Standard (IMIS) being promoted by the 3D-IC Alliance recently released its official specification for 3-D stacking memory chips.
Founding members of the Alliance, Tezzaron Semiconductor Corp. (Naperville, Ill.) and Ziptronix, Inc. (Morrisville, N.C.), are already fabricating memory chips using the IMIS port, the first versions of which will be available by the end of 2008.
"Today's high-speed processor cores need a 3-D interconnect with very high sustained bandwidth that is beyond any existing or planned DDR memory technology," said Robert Patti, CEO of Tezzaron.
Owing to the low capacitance of the "intimate" connection achieved by stacking a memory die atop a processor die, power consumption is about 24 microwatts per pin compared to 30-40 millwatts per pin for DDR. That low-power in IMIS's 1,000-pin parallel connection between processor and memory limits power consumption to less that 3 watts, compared to over 30 watts for conventional interconnects.
"We believe that IMIS solves the processor makers' bandwidth problems to [acheiving] multigigabit memories--typical access times to our DRAMs is seven nanoseconds," said Patti. "We are getting DRAM densities at near SRAM speeds and better than DRAM costs."
The IMIS port measures 450 by 2,000 microns and contains a pin grid that is 19 cells high by 80 cells wide, each cell measuring 25 microns2. Processor manufacturers modifying their dies to include an IMIS port will be able to add compatible memory chips from any member of the 3D-IC Alliance, which includes about a half dozen members.