MONTEREY, Calif. -- Photomask complexity is outstripping the compute power in today's mask shops, prompting the need for new technologies like computational lithography and other schemes, according to the top executive at Synopsys Inc.
During a keynote address at the SPIE Photomask Technology conference here on Tuesday, Aart de Geus, chairman and CEO of EDA giant Synopsys (Mountain View, Calif.), also listed five ways for chip makers to reduce their overall IC design costs.
Here's the magic list from the Synopsys executive: fewer IC design flows; systematic verification; systematic IP re-use; platform-based design; and structured software development methodologies.
Many of these concepts are not new and have been talked about for some time. In any case, IC design--and process costs--are soaring out of control at each technology node. In total, process R&D costs are about $800 million for the 45-nm node and around $1.1 billion at 32-nm, he said.
"From a design point of view, it's not getting any cheaper," de Geus said. "Verification is growing so massively."
Verification remains the single biggest problem in chip design. It remains time consuming and expensive.
Another ongoing issue is the complexity of the lowly photomask. The overall cost of the photomask remains relatively flat, but the complexity--such as the resolution enhancement techniques (RETs) in masks--are growing at a stunning rate of 40 percent a year, he said. The problem is that overall compute power within the mask shops cannot keep pace with RETs and optical proximity correction (OPC), he said.
To solve the issue, de Gues briefly mentioned the new buzzword in the industry: computational lithography. In fact, several companies are scrambling to develop the technology and for good reason.
For example, IBM Corp. and Mentor Graphics Corp. are working on computational lithography for the 22-nm node. That's because next-generation lithography solutions, such as EUV, maskless and nanoimprint, will not be ready for the 22-nm node.
Computational lithography is more of a software solution. ''Computational lithography is a method of overcoming limitations in the manufacturing process by using computationally-intensive numerical methods to modify the shape of the masks and characteristics of the illuminating source at each layer of an IC in such a way that the result after exposure is closer to the intended shapes,'' according to a recent release from IBM Corp.. ''One popular computational lithography technique is optical proximity correction.''