Design techniques intended to curb power in modern semiconductor devices can introduce bugs that cause silicon to fail. Failed silicon, in turn, can delay product introductions, resulting in lost market opportunities and revenue.
Thorough verification of low-power techniques prior to tape-out is vital to avoid nasty surprises down the road. But this increased complexity has verification teams scrambling to stay on schedule—the infamous design-verification gap is growing even larger. To ensure the success of a low-power project, it's essential to constantly gather and analyze coverage and assess verification progress.
A low-power design can operate in one of many power modes—for example, Light, Sleep, Idle and Active modes. In each mode, one or more blocks can be shut on or off, have its contents retained or restored, or simply remain in standby.
Comprehensive verification of a low-power design involves ensuring that the design operates in accordance with the design specification in all power states, and that all intended power-mode transitions and sequences happen as expected. Coverage of a low-power design is a measure that the testbenches have exercised all the power modes, transitions and sequences.
Think of the power modes, transitions and sequences for a low-power design as a power finite state machine (FSM). The power FSM can capture the logic states that are part of a transition from one power mode to another. For every design, the power intent reduces to a power FSM, and the verification task is to completely verify the power FSM.