SAN JOSE, Calif. Samsung will describe 4 and 8 Gbit DRAM chips, and a team from Toshiba and SanDisk will detail a 64 Gbit NAND flash chip packing four bits per cell at the International Solid State Circuits Conference in February. The 8 Gbit DRAM is one of many chips to be described at the event using vertical stacking techniques.
Also at ISSCC, Intel will describe an eight-core x86 server chip using a whopping 2.3 billion transistors. Intel will dominate the session on microprocessors with four of eight papers, none from rivals such as Advanced Micro Devices, IBM or Sparc partners Fujitsu and Sun Microsystems.
Samsung will detail a design that stacks four 2 Gbit DDR3 DRAMs using through silicon vias. The paper will describe new check and repair techniques for the vias that boost yield by 15 to 98 percent.
The stacking technique is increasingly seen as a key tool for tomorrow's system-in-package devices. In a separate paper, Toshiba will describe its use of through silicon vias to create a CMOS imager module that significantly reduces the size and cost compared to existing chips.
A team from Irvine Sensors, Forza Silicon and MIT Lincoln Lab will present a paper on a Mpixel CMOS sensor that includes a stack of 2x32-channel analog digital converters. The use of such stacking techniques in imagers should being lower cost, high performance cameras to mobile devices, said ISSCC organizers.
Separately, NEC will describe a novel approach to 3-D chip stacking that links an SRAM and system-on-chip dice by electrodes with a 10 micron pitch. The approach replaces micro-bumps with 50 micron pitches.
On the memory front, a team of researchers from Toshiba and SanDisk will describe a 64 Gbit NAND flash chip that packs four-bits per cell using a technique that creates 16 distinct storage levels. The chip is made in a 43nm process and can write at speeds up to 5.6 Mbits/second using a three-step programming method.
"Achieving 16 levels of discrimination in a flash cell is a very analog problem that's pretty interesting," said Ken Smith, one of the ISSCC organizers.
For its part, Samsung will also describe a 4 Gbit DDR3 DRAM running at 1.2 V. It is made in a 56 nm process and supports throughput up to 1.6 Gbits/s/pin.
Intel will kick off a session on microprocessors that includes three papers on its recently announced Nehalem family of CPUs and one on the clocking scheme for a quad-core Itanium processor. At 2.3 billion transistors, the eight-core Nehalem processor is the most dense chip described at ISSCC to date. Intel has said it will ship in late 2009.
Intel authored a number of papers at the event including one that will give a peak into its 32 nm process technology. That paper will detail a 291 Mbit SRAM chip that runs at up to 4 GHz at 1V, made in Intel's 32nm high-K metal gate process.
Another Intel paper will describe the optical interconnects used on its Tera-Scale Computing R&D chip that debuted at last year's event. Nudging closer to terahertz devices, a team from NXP Semiconductors, Texas Instruments and the University of Florida will report at ISSCC 2009 on work designing an 800 GHz CMOS phase-locked loop, a building block for future Terahertz-class systems.