BERKELEY, Calif. Researchers officially christened the Parallel Computing Lab here Monday (Dec. 1) in a newly renovated space at the University of California, Berkeley. The center has been conducting work for several months to define a new parallel programming model for tomorrow's many-core processors that could replace serial methods that have served mainstream computing since its inception.
"We have the opportunity to reset the software stack for the next 30 years," said David A. Patterson, veteran Berkeley computer science professor and director of the lab. "I can't think of another research project that has as much upside or risk," he added.
The Berkeley lab is exploring everything from novel chip architectures to new parallel applications as well as all the parallel languages, runtime environments and test and emulation tools needed to created them. It is one of two efforts funded jointly by Intel and Microsoft, splitting $20 million over five years--the other lab being located at the University of Illinois.
Other universities, most notably Stanford in nearby Palo Alto, have launched parallel computing labs to tackle technical issues underlying the historic shift.
At the opening, Pat Gelsinger, general manager of Intel's digital enterprise group, talked about his work in 2002 that led to Intel's decision to embrace multicore parallelism as the future for its microprocessors. He also shared an anecdote about difficulties he had convincing Microsoft chairman Bill Gates about the need and significance of the shift away from fast serial pipelines.
Microsoft is clearly backing the trend today, with parallel computing experts Burton Smith and Daniel Reed leading the many-core charge for the Windows giant.
Tony Hey, a Microsoft executive who oversees the company's external research efforts, talked about his work coordinating the competition that selected Berkeley and the University of Illinois as sites for the parallel computing research. Hey also talked about his work as a former developer of the Transputer, an early parallel processor, and a co-developer of MPI, a widely used parallel programming model for high-end technical computing.
The fifth floor of Berkeley's Soda Hall was renovated to house the lab, using an open floor plan to maximize interactions between faculty and graduate students. The concept was influenced by Berkeley's RAD lab, itself influenced by the layout of companies such as Google that prize collaboration.
"The highest purpose of this space is to inspire innovation, and that's a tall order for a renovation project," said Patterson.
He said labs run the risk of becoming "DSL deserts" as researchers telecommute over broadband lines. "I don't know of that's good for product development, but it's deadly for research," he added.
Graduate students presented more than a dozen poster sessions at the opening describing their work to date.
One of the students, Christopher Batten, described 65nm test chips that created in CMOS an optical waveguide, modulator and filter that could help form an optical interface between a 256-core processor and 16 DRAM modules. The initial effort only defined single hop point-to-point links that did not use optical switching and thus does not deliver on the full bandwidth potential of optical connections.
"There are a lot of hurdles, and this is just a first step," Batten said.
Another grad student, Greg Gibeling, described a next-generation of Berkeley's RAMP emulator that could be used to test new parallel hardware concepts. The so-called RAMP Gold will use a multithreaded Sparc instruction set to let researchers run applications software over parallel processors simulated on an array of Xilinx Virtex FPGAs.