OTTAWA With 32-nm process technology less than a year away from entering production, both Intel Corp. and IBM Corp. will provide details about their technologies during the 2008 IEEE International Electron Devices Meeting in San Francisco. IEDM also will offer a glimpse down the semiconductor roadmap, including the 22-nm production node.
As for 32 nm, Intel will present details of its technology first announced in September 2007 at the Intel Developer Forum. Sanjay Natarajan, manager of Intel's 32-nm CMOS technology development, demonstrated a fully functional 291-Mbit SRAM test chip. Intel will update it progress in 32-nm development at IEDM.
Intel's 32-nm process continues on the path laid down with the introduction of the high-k metal gate stack at 45 nm. The second-generation high-k dielectric is scaled down to improve transistor performance while aiding SRAM scaling. Intel also dives into immersion lithography at 32 nm.
Intel claims world records for drive current and gate pitch. The NMOS drive current is 1.55mA/m, or about a 14 percent improvement over 1.36mA/m at 45 nm.
The 32-nm process achieves about 70 percent linear scaling to reach the best reported gate pitch of 112.5 nm, thereby keeping Moore's Law on track. The gate pitch cited in Intel's IEDM paper is actually a 3-percent shrink from their first SRAM test chip. That shrink also enabled an SRAM cell size reduction from 0.182 down to the 0.171 microns2, something Natarajan will describe at IEDM.
Intel Senior Fellow Mark Bohr said he remains confident that Intel's 32-nm process will be ready for volume production during the fourth quarter of 2009, although ramp up ultimately depends on when microprocessor product managers switch to the next node.
Given its track record, it wouldn't be surprising if Intel's 32-nm technology was delayed beyond the end of 2009. That would be two years after 45 nm arrived, maintaining the sequence of Intel's process node introductions.
An Steegen, IBM's manager for 32-nm bulk technology Development, will present details of its 32-nm foundry technology. IBM will offer both a low-power, high-performance flavor of their 32-nm bulk process. IBM first unveiled a low-power 32-nm technology on silicon-on-insulator at the VLSI Symposium earlier this year. With IBM's shift to a high-k metal gate process, Steegan and her team will focus on scaling and optimizing both effective electrical thickness of the gate dielectric as well as the physical gate length.