In the low-power version of IBM's 32-nm bulk process, no strain engineering techniques were used. In the high-performance process, standard stressors enhanced the baseline transistor. Actual transistor performance metrics of the drive current and leakage will be presented during IEDM.
IBM's 32-nm team is quick to point out that their gate-first approach to high-k continues conventional design rules for the physical design of circuits. Foundry customers will not be faced with restrictions on design rules. The gate-first high-k stack takes advantage of the maturity of polysilicon gate processing while introducing advanced materials to improve transistor performance.
IBM's process also uses a single metal gate with different interface layer materials to set the workfunction for NMOS and PMOS transistors.
IBM said it expects the market to develop earlier for the low-power version of its 32-nm bulk process. Therefore, it plans to have it ready for production late in 2009. The high-performance version with strained silicon won't arrive until 2010. IBM is running multiproduct wafers now, and expects to get silicon into the hands of customers in February.
Taking a longer view of the semiconductor roadmap, IBM will announce at IEDM what it claims in the world's smallest reported SRAM cell size: 0.1 microns2. Bruce Doris, IBM's manager of device integration research at Albany
Nanotech, said the device also is "an important proof-of-concept that planar CMOS technology using conventional techniques can produce working SRAM at 22 nanometers."
Although the 22-nm team hopes to push conventional tungsten contact plugs as far as possible, their cell was built using damascene copper contacts. The researchers are also investigating both copper and tungsten contact approaches, but the copper contact process was ready in time to create the demonstration devices.
IBM's SRAM layout demanded a contact window of only 25 nm to match its 25-nm gate lengths.
The Albany group provided early research for IBM's process development teams in East Fishkill, N.Y. The 22-nm research chips were made using production 300-mm tools at Albany Nanotech. Doris claims his team has produced even smaller SRAM bit cells.
Intel Fellow Kelin Kuhn will teach one module of an IEDM short course, "22-nm CMOS Technology." Kuhn will provide her insights into 22-nm device architecture and performance elements.