SAN FRANCISCOCMOS device process variability remains one of the most acute problems facing the semiconductor industry, particularly at the 45-nm node and beyond, according to presenters Tuesday (Dec. 16) at the International Electron Devices Meeting (IEDM).
Random defects were the primary cause of manufacturing yield loss up to the 130-nm node, when layout systematic effects became more critical, according to a paper presented by Andrez Strojwas of Carnegie-Mellon University and PDF Solutions Inc. But more recently, Strojwas said, due to challenging product performance requirements and increased process variability, parametric yield losses have also become significant.
Strojwas's paper, "Taking the next step in Moore's Law: Design's turn to enable next technology node," prescribed a regular layout methodology for 32-nm and below, including the creation of a design fabric with a limited number of "printability friendly patterns" that enable the co-optimization of circuit, process and design. This approach calls for limited layour contacts and construct-specific rules, Strojwas said.
This methodology, known as pdBRIX, was originally developed by startup Fabbrix Inc., which was backed by Carnegie-Mellon. Fabbrix was
acquired in May 2007 by PDF Solutions, which markets the technology under the name pdBRIX.
Some have argued that so-called restrictive design approaches like pdBRIX limit designers' creativity, forcing them to design within constraints established to ensure higher yield. Strojwas acknowledged this argument in his talk Tuesday, but suggested that designers' creativity is already beginning constrained by process variability's impact on yield.
Strojwas said the adoption of high-k metal gate for 32-nm would help reduce process variability, at least for one node. He said the pdBRIX methodology would enable single-pass lithography at the 32-nm node. It has been widely assumed that the 32-nm node would require double patterning lithography.