SAN FRANCISCO -- At the International Solid-State Circuits Conference (ISSCC) here, Toshiba Corp. will describe a high-density, 128-megabit ferroelectric random access memory (FeRAM or FRAM).
Based on a 130-nm process, the new chip from Toshiba (Tokyo) is said to have a cell size of 0.252-um2, read and write speeds of 1.6-gigabytes a second, 83-ns cycle times and 43-ns access times.
The new FeRAM modifies Toshiba's so-called ChainFeRAM architecture, which enables chip scaling. One of the major problems with FeRAMs and other next-generation, non-volatile memories are the ability to scale.
Due to those and other limitations, FeFRAMs have been relegated to niche applications--they are mainly aimed to replace SRAMs in embedded systems. Still others claim FeRAMs are the next possible ''universal memory.''
FeRAMs, according to Toshiba, combine the fast operating characteristics of DRAM with the non-volatile capabilities of flash memory. Fujitsu, Ramtron, TI, Toshiba and others are devising FeRAMs.
In developing the new FeRAM, Toshiba broke its own record of 32-Mbit density and 200-megabites-a-second data transfers, pushing performance to eight times faster than the transfer rate of the previous records and the fastest speed of any non-volatile RAM. The new 128-Mbit device is said to be the most advanced combination of performance and density yet achieved for a non-volatile memory, according to Toshiba.
Meanwhile, chip scaling causes signal degradation as the stored polarization of memory cell gets smaller. To solve the issue in FeRAMs, Toshiba has devised the ChainFeRAM technology.
In the earlier generation of 64-Mbit devises, FeRAM ''employed a data-line design in which neighboring data-lines operated in sequence: one is off when the other is on,'' according to Toshiba.
''This allowed off lines to provide a noise barrier between on lines, contributing to chip scaling and fine performance. Previous chain architecture collected four data-lines but Toshiba has successfully increased the number of data-lines to eight, which led to a decrease in the total chip area,'' according to Toshiba.
With the technology, Toshiba maintained the same cell signal level without any chip area penalty. Furthermore, improvement of the sensing technique reduced the parasitic capacitance and realized a reading signal of 200-mV.