SAN FRANCISCOSynopsys Inc. has launched a verification IP alliance program with a goal of providing designers with access to a broader range of Verification Methodology Manual (VMM)-enabled verification IP.
Initial members in the DesignWare VIP Alliance program include eInfochips, a spec-to-system solutions company, and NoBug, a digital design, verification and EDA company, Synopsys (Mountain View, Calif.) said. Both are members of the Synopsys VMM Catalyst Program.
Establishing a network of pre-qualified VIP vendors will designers accelerate and simplify the verification of IP blocks in SoCs with less risk and faster time to results, Synopsys said.
The VMM for SystemVerilog is a reference book intended to help designers architect SystemVerilog verification environments.
The verification IP offered by the partners through the DesignWare VIP Alliance will be developed in accordance with the guidelines used by Synopsys' verification IP engineering experts, according to the company.
HDMI Verification IP is available immediately through the DesignWare VIP Alliance, Synopsys said.